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| features ? high-performance, low-power avr ? 8-bit microcontroller ? risc architecture ? 118 powerful instructions ? most single clock cycle execution ? 32 x 8 general purpose working registers ? fully static operation ? up to 16 mips throughput at 16 mhz ? data and non-volatile program memory ? 2k bytes of in-system programmable program memory flash endurance: 10,000 write/erase cycles ? 128 bytes of in-system programmable eeprom endurance: 100,000 write/erase cycles ? 128 bytes internal sram ? programming lock for flash pr ogram and eeprom data security ? peripheral features ? 8-bit timer/counter wi th separate prescaler ? 8-bit high-speed timer with separate prescaler 2 high frequency pwm outputs with separate output compare registers non-overlapping inverted pwm output pins ? universal serial interface wi th start condition detector ? 10-bit adc 11 single ended channels 8 differential adc channels 7 differential adc channel pairs wi th programmable gain (1x, 20x) ? on-chip analog comparator ? external interrupt ? pin change interrupt on 11 pins ? programmable watchdog timer with separate on-chip oscillator ? special microcontroller features ? low power idle, noise reduction, and power-down modes ? power-on reset and programmable brown-out detection ? external and internal interrupt sources ? in-system programmable via spi port ? internal calibrated rc oscillator ? i/o and packages ? 20-lead pdip/soic: 16 programmable i/o lines ? 32-lead qfn/mlf: 16 pr ogrammable i/o lines ? operating voltages ? 2.7v - 5.5v for attiny26l ? 4.5v - 5.5v for attiny26 ? speed grades ? 0 - 8 mhz for attiny26l ? 0 - 16 mhz for attiny26 ? power consumption at 1 mhz, 3v and 25 c for attiny26l ? active 16 mhz, 5v and 25 c: typ 15 ma ? active 1 mhz, 3v and 25 c: 0.70 ma ? idle mode 1 mhz, 3v and 25 c: 0.18 ma ? power-down mode: < 1 a 8-bit microcontroller with 2k bytes flash attiny26 attiny26l 1477i?avr?10/06
2 attiny26(l) 1477i?avr?10/06 pin configuration note: the bottom pad under the qfn/mlf package should be soldered to ground. 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 (mosi/di/sda/oc1a) pb0 (miso/do/oc1a) pb1 (sck/scl/oc1b) pb2 (oc1b) pb3 vcc gnd (adc7/xtal1) pb4 (adc8/xtal2) pb5 (adc9/int0/t0) pb6 (adc10/reset) pb7 pa0 (adc0) pa1 (adc1) pa2 (adc2) pa3 (aref) gnd avcc pa4 (adc3) pa5 (adc4) pa6 (adc5/ain0) pa7 (adc6/ain1) pdip/soic 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 mlf top view nc (oc1b) pb3 nc vcc gnd nc (adc7/xtal1) pb4 (adc8/xtal2) pb5 nc pa2 (adc2) pa3 (aref) gnd nc nc avcc pa4 (adc3) nc (adc9/int0/t0) pb6 (adc10/reset) pb7 nc (adc6/ain1) pa7 (adc5/ain0) pa6 (adc4) pa5 nc pb2 (sck/scl/oc1b) pb1 (miso/do/oc1a) pb0 (mosi/di/sda/oc1a) nc nc nc pa0 (adc0) pa1 (adc1) 3 attiny26(l) 1477i?avr?10/06 description the attiny26(l) is a low-power cmos 8-bit microcontroller based on the avr enhanced risc architecture. by executing powe rful instructions in a single clock cycle, the attiny26(l) achieves throughputs approaching 1 mips per mhz allowing the system designer to optimize power consum ption versus processing speed. the avr core combines a rich instruction se t with 32 general purpose working registers. all the 32 registers are directly connected to the arithmetic logic unit (alu), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. the resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional cisc microcontrollers. the attiny26(l) has a high precision adc with up to 11 single ended channels and 8 differential channels. seven differential channels have an optional gain of 20x. four out of the seven differential channels, which have the optional gain, can be used at the same time. the attiny26(l) also has a high frequency 8-bit pwm module with two independent outputs. two of the pwm outputs have inverted non-overlapping output pins ideal for synchronous rectifica- tion. the universal serial interface of the attiny26(l) allows efficient software implementation of twi (two-wire serial interf ace) or sm-bus interface. these features allow for highly integrated battery charger an d lighting ballast applic ations, low-end ther- mostats, and firedetectors, among other applications. the attiny26(l) provides 2k bytes of flash, 128 bytes eeprom, 128 bytes sram, up to 16 general purpose i/o lines, 32 general purpose working registers, two 8-bit timer/counters, one with pwm outputs, internal and external oscillators, internal and external interrupts, programmable watchdog timer, 11-channel, 10-bit analog to digital converter with two differential voltage input gain stages, and four software selectable power saving modes. the idle mode stops the cpu while allowing the timer/counters and interrupt system to continue functioning. the attiny26(l) also has a dedicated adc noise reduction mode for reducing the noise in adc conversion. in this sleep mode, only the adc is functioning. the power-down mode saves the register contents but freezes the oscillators, disabling all other ch ip functions until the next interrupt or hard- ware reset. the standby mode is the same as the power-down mode, but external oscillators are enabled. the wakeup or interrupt on pin change features enable the attiny26(l) to be highly res ponsive to external events, st ill featuring the lowest power consumption while in the power-down mode. the device is manufactured using atmel?s high density non-volatile memory technology. by combining an enhanced risc 8-bit cpu with flash on a monolithic chip, the attiny26(l) is a powerful microcontroller that provides a highly flexible and cost effec- tive solution to many embedded control applications. the attiny26(l) avr is supported with a full suite of program and system development tools including: macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits. 4 attiny26(l) 1477i?avr?10/06 block diagram figure 1. the attiny26(l) block diagram watchdog timer mcu control register universal serial interface timer/ counter0 data dir. reg.port a data register port a programming logic timing and control timer/ counter1 mcu status register port a drivers pa0-pa7 vcc gnd + - analog comparator 8-bit data bus adc isp interface interrupt unit eeprom internal oscillator oscillators calibrated oscillator internal data dir. reg.port b data register port b port b drivers pb0-pb7 program counter stack pointer program flash sram general purpose registers instruction register instruction decoder status register z y x alu control lines avcc 5 attiny26(l) 1477i?avr?10/06 pin descriptions vcc digital supply voltage pin. gnd digital ground pin. avcc avcc is the supply voltage pin for port a and the a/d converter (adc). it should be externally connected to v cc , even if the adc is not used. if the adc is used, it should be connected to v cc through a low-pass filter. see page 96 for details on operating of the adc. port a (pa7..pa0) port a is an 8-bit general purpose i/o port. pa7..pa0 are all i/o pins that can provide internal pull-ups (selected fo r each bit). port a has alter nate functions as analog inputs for the adc and analog comparator and pin change interrupt as described in ?alternate port functions? on page 48. port b (pb7..pb0) port b is an 8-bit general purpose i/o port. pb6..0 are all i/o pins that can provide inter- nal pull-ups (selected for each bit). pb7 is an i/o pin if not used as the reset. to use pin pb7 as an i/o pin, instead of reset pin, program (?0?) rstdisbl fuse. port b has alternate functions for the adc, clocking, timer counters, usi, spi programming, and pin change interrupt as described in ?alternate port functions? on page 48. an external reset is generated by a low level on the pb7/reset pin. reset pulses longer than 50 ns will generate a reset, even if the clock is not running. shorter pulses are not guaranteed to generate a reset. xtal1 input to the inverting oscillato r amplifier and input to the in ternal clock operating circuit. xtal2 output from the invert ing oscillator amplifier. 6 attiny26(l) 1477i?avr?10/06 resources a comprehensive set of development tools, application notes and datasheets are avail- able for download on http://www.atmel.com/avr. 7 attiny26(l) 1477i?avr?10/06 about code examples this datasheet contains simp le code examples that brie fly show how to use various parts of the device. these code examples assume that the part specific header file is included before compilation. be aware that not all c compiler vendors include bit defini- tions in the header files and interrupt handling in c is compiler dependent. please confirm with the c compiler documentation for more details. 8 attiny26(l) 1477i?avr?10/06 avr cpu core architectural overview the fast-access register file concept contains 32 x 8-bit general purpose working reg- isters with a single clock cycle access time. this means that during one single clock cycle, one alu (arithmetic logic unit) operation is executed. two operands are output from the register file, the operation is executed, and the result is stored back in the register file ? in one clock cycle. six of the 32 registers can be used as 16-bit pointers for indirect memory access. these pointers are called the x-, y-, and z-pointers, and they can address the register file and the flash program memory. figure 2. the attiny26(l) avr enhanced risc architecture the alu supports arithmetic and logic functions between registers or between a con- stant and a register. single register operat ions are also executed in the alu. figure 2 shows the attiny26(l) avr enhanced risc mi crocontroller architecture. in addition to the register operation, the conventional memory addressing modes can be used on the register file as well. this is enabled by the fact that the register file is assigned the 32 lowermost data space addresses ($00 - $1f), allowing them to be accessed as though they were ordinary memory locations. the i/o memory space contains 64 addresse s for cpu peripheral functions as control registers, timer/counters, a/d converters, and other i/o functions. the i/o memory can be accessed directly, or as the data space locations following those of the register file, $20 - $5f. 1024 x 16 program flash instruction register instruction decoder program counter control lines 32 x 8 general purpose registers alu direct addressing indirect addressing status and test control registers interrupt unit 2 x 8-bit timer/counter universal serial interface watchdog timer analog comparator i/o lines 8-bit data bus isp unit adc 128 x 8 sram 128 byte eeprom 9 attiny26(l) 1477i?avr?10/06 the avr uses a harvard architecture concept with separate memories and buses for program and data memories. the program memory is accessed with a two stage pipelining. while one instruction is being executed, the next instruction is pre-fetched from the program memory. this concept enables instructions to be executed in every clock cycle. the program memory is in-system programmable flash memory. with the relative jump and relative call in structions, the whole address space is directly accessed. all avr instructions have a single 16-bit word format, meaning that every program memory address contains a single 16-bit instruction. during interrupts and subroutine calls, the return address program counter (pc) is stored on the stack. the stack is effectively allocated in the general data sram, and consequently the stack size is only limited by the total sram size and the usage of the sram. all user programs must initialize the sp in the reset routine (before subroutines or interrupts are executed). the 8-bit stack pointer sp is read/write accessible in the i/o space. for programs written in c, the stack size must be declared in the linker file. refer to the c user guide for more information. the 128 bytes data sram can be easily acce ssed through the five different addressing modes supported in the avr architecture. the memory spaces in the avr architecture are all linear and regular memory maps. the i/o memory space contains 64 addresse s for cpu peripheral functions as control registers, timer/counters, and other i/o functions. the memory spaces in the avr architecture are all linear and regular memory maps. a flexible interrupt module has its control registers in the i/o space with an additional global interrupt enable bit in the status register. all the different interrupts have a sep- arate interrupt vector in the interrupt vector table at the beginning of the program memory. the different interrupts have priority in accordance with their interrupt vector position. the lower the interrupt vector address, the higher the priority. general purpose register file figure 3 shows the structure of the 32 general purpose working registers in the cpu. figure 3. avr cpu general purpose working registers 7 0 addr. r0 $00 r1 $01 r2 $02 ? r13 $0d general r14 $0e purpose r15 $0f working r16 $10 registers r17 $11 ? r26 $1a x-register low byte r27 $1b x-register high byte r28 $1c y-register low byte r29 $1d y-register high byte r30 $1e z-register low byte r31 $1f z-register high byte 10 attiny26(l) 1477i?avr?10/06 all of the register operating instructions in the instruction set have direct and single cycle access to all registers. the only exceptions are the five constant arithmetic and logic instructions sbci, subi, cpi, andi, and ori between a constant and a register, and the ldi instruction for load immediate constant data. these instructions apply to the second half of the registers in the register file ? r16..r31. the general sbc, sub, cp, and, and or, and all other operations between two registers or on a single register apply to the entire register file. as shown in figure 3, each register is also assigned a data memory address, mapping them directly into the first 32 locations of the user data space. although not being phys- ically implemented as sram locations, this memory organization provides flexibility in access of the registers, as the x-, y-, and z-registers can be set to index any register in the file. x-register, y-register, and z- register the registers r26..r31 have some added f unctions to their general purpose usage. these registers are address pointers for indirect addressing of the data space. the three indirect address registers x, y, and z are defined as: figure 4. x-, y-, and z-register in the different addressing modes, these address registers have functions as fixed dis- placement, automatic increment and decrement (see the descriptions for the different instructions). alu ? arithmetic logic unit the high-performance avr alu operates in direct connection with all 32 general pur- pose working registers. within a single clock cycle, alu operations between registers in the register file are executed. the alu operations are divided into three main catego- ries ? arithmetic, logical, and bit-functions. 15 0 x-register 7 0 7 0 r27 ($1b) r26 ($1a) 15 0 y-register 7 0 7 0 r29 ($1d) r28 ($1c) 15 0 z-register 7 0 7 0 r31 ($1f) r30 ($1e) 11 attiny26(l) 1477i?avr?10/06 status register ? sreg the avr status register ? sreg ? at i/o space location $3f is defined as: ? bit 7 ? i: global interrupt enable the global interrupt enable bit must be set (one) for the interrupts to be enabled. the individual interrupt enable control is then performed in the interrupt mask registers ? gimsk and timsk. if the global interrupt enable register is cleared (zero), none of the interrupts are enabled independent of the gimsk and timsk values. the i-bit is cleared by hardware after an interrupt has occurred, and is set by the reti instruction to enable subsequent interrupts. the i-bit can also be set and cleared by the application with the sei and cli instructions, as described in the instruction set reference. ? bit 6 ? t: bit copy storage the bit copy instructions bld (bit load) and bst (bit store) use the t-bit as source and destination for the operated bit. a bit from a register in the register file can be cop- ied into t by the bst instruction, and a bit in t can be copied into a bit in a register in the register file by the bld instruction. ? bit 5 ? h: half carry flag the half carry flag h indicates a half carr y in some arithmetic operations. see the instruction set descriptio n for detailed information. ? bit 4 ? s: sign bit, s = n v the s-bit is always an exclusive or between the negative flag n and the two?s comple- ment overflow flag v. see the instruction set description for detailed information. ? bit 3 ? v: two?s complement overflow flag the two?s complement overflow flag v supports two?s complement arithmetics. see the instruction set descripti on for detailed information. ? bit 2 ? n: negative flag the negative flag n indicates a negative result after the different arithmetic and logic operations. see the instruction set description for detailed information. ? bit 1 ? z: zero flag the zero flag z indicates a zero result after the different arithmetic and logic opera- tions. see the instruction set description for detailed information. ? bit 0 ? c: carry flag the carry flag c indicates a carry in an arithmetic or logic operation. see the instruction set description for detailed information. bit 76543210 $3f ($5f) i t h s v n z c sreg read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 12 attiny26(l) 1477i?avr?10/06 stack pointer ? sp the attiny26(l) stack pointer is implemented as an 8-bit register in the i/o space loca- tion $3d ($5d). as the attiny26(l) data memory has 224 ($e0) locations, eight bits are used. the stack pointer points to the data sram stack area where the subroutine and inter- rupt stacks are located. this stack space in the data sram must be defined by the program before any subroutine calls are executed or interrupts are enabled. the stack pointer must be set to point above $60. the stack pointer is decremented by one when data is pushed onto the stack with the push instruction, and it is decremented by two when an address is pushed onto the stack with subroutine calls and interrupts. the stack pointer is incremented by one when data is popped from the stack with the pop instruction, and it is incremented by two when an address is popped from the stack with return from subroutine ret or return from interrupt reti. program and data addressing modes the attiny26(l) avr enhanced risc microcontroller supports powerful and efficient addressing modes for access to the flash program memory, sram, register file, and i/o data memory. this section describes the different addressing modes supported by the avr architecture. in the figures, op means the operation code part of the instruction word. to simplify, not all figures show th e exact location of the addressing bits. register direct, single register rd figure 5. direct single register addressing the operand is contained in register d (rd). bit 76543210 $3d ($5d) sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 sp read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 13 attiny26(l) 1477i?avr?10/06 register direct, two registers rd and rr figure 6. direct register addressing, two registers operands are contained in register r (rr) and d (rd). the result is stored in register d (rd). i/o direct figure 7. i/o direct addressing operand address is contained in 6 bits of th e instruction word. n is the destination or source register address. data direct figure 8. direct data addressing op rr/rd 16 31 15 0 16 lsbs $0000 $00df 20 19 data space 14 attiny26(l) 1477i?avr?10/06 a 16-bit data address is contained in the 16 lsbs of a two-word instruction. rd/rr specify the destination or source register. data indirect with displacement figure 9. data indirect with displacement operand address is the result of the y- or z-register contents added to the address con- tained in 6 bits of the instruction word. data indirect figure 10. data indirect addressing operand address is the contents of the x-, y-, or the z-register. data indirect with pre- decrement figure 11. data indirect addressing with pre-decrement data space $0000 $00df y or z - register op a n 0 0 5 6 10 15 15 data space $0000 $00df x-, y-, or z-register 0 15 data space $0000 $00df x-, y-, or z-register 0 15 -1 15 attiny26(l) 1477i?avr?10/06 the x-, y-, or z-register is decremented before the operation. operand address is the decremented contents of the x-, y-, or z-register. data indirect with post- increment figure 12. data indirect addressing with post-increment the x-, y-, or z-register is incremented after the operation. operand address is the con- tent of the x-, y-, or z-register prior to incrementing. constant addressing using the lpm instruction figure 13. code memory constant addressing constant byte address is specified by the z-register contents. the 15 msbs select word address (0 - 1k), the lsb selects low byte if cleared (lsb = 0) or high byte if set (lsb = 1). data space $0000 $00df x-, y-, or z-register 0 15 1 $3ff $000 program memory 16 attiny26(l) 1477i?avr?10/06 indirect program addressing, ijmp and icall figure 14. indirect program memory addressing program execution continues at address contained by the z-register (i.e., the pc is loaded with the contents of the z-register). relative program addressing, rjmp and rcall figure 15. relative program memory addressing program execution continues at address pc + k + 1. the relative address k is from -2048 to 2047. $3ff $000 program memory $3ff $000 program memory +1 17 attiny26(l) 1477i?avr?10/06 memories the avr cpu is driven by the system cloc k ?, directly generated from the external clock crystal for the chip. no in ternal clock division is used. figure 16 shows the parallel instruction fetches and instruction executions enabled by the harvard architecture and the fast-access register file concept. this is the basic pipelining concept to obtain up to 1 mips per mhz with the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit. figure 16. the parallel instruction fetches and instruction executions figure 17 shows the internal timing concept for the register file. in a single clock cycle an alu operation using two register operands is executed, and the result is stored back to the destination register. figure 17. single cycle alu operation the internal data sram access is performed in two system clock cycles as described in figure 18. system clock ? 1st instruction fetch 1st instruction execute 2nd instruction fetch 2nd instruction execute 3rd instruction fetch 3rd instruction execute 4th instruction fetch t1 t2 t3 t4 system clock ? total execution time register operands fetch alu operation execute result write back t1 t2 t3 t4 18 attiny26(l) 1477i?avr?10/06 figure 18. on-chip data sram access cycles in-system programmable flash program memory the attiny26(l) contains 2k bytes on-chip in-system programmable flash memory for program storage. since all instructions are 16- or 32-bit words, the flash is organized as 1k x 16. the flash memory has an endurance of at least 10,000 write/erase cycles. the attiny26(l) program counter ? pc ? is 10 bits wide, thus addressing the 1024 program memory addresses, see ?memory programming? on page 109 for a detailed description on flash data downloading. see ?program and data addressing modes? on page 12 for the different program memory addressing modes. figure 19. sram organization sram data memory figure 19 above shows how the attiny 26(l) sram memory is organized. the lower 224 data memory locations address the register file, the i/o memory and the internal data sram. the first 96 locations address the register file and i/o mem- ory, and the next 128 locations address the internal data sram. system clock ? wr rd data data address address t1 t2 t3 t4 prev. address read write register file data address space r0 $0000 r1 $0001 r2 $0002 ... ... r29 $001d r30 $001e r31 $001f i/o registers $00 $0020 $01 $0021 $02 $0022 ? ? $3d $005d $3e $005e $3f $005f internal sram $0060 $0061 ... $00de $00df 19 attiny26(l) 1477i?avr?10/06 the five different addressing modes for the data memory cover: direct, indirect with dis- placement, indirect, indirect with pre-decrement, and indirect with post-increment. in the register file, registers r26 to r31 feature the indirect addressing pointer registers. the direct addressing reaches the entire data space. the indirect with displacement mode features a 63 address locations reach from the base address given by the y- or z- register. when using register indirect addressing modes with automatic pre-decrement and post- increment, the address registers x, y, and z are decremented and incremented. the 32 general purpose working registers, 64 i/o registers and the 128 bytes of inter- nal data sram in the attiny26(l) are all accessible through all these addressing modes. see ?program and data addressing modes? on page 12 for a detailed description of the different addressing modes. eeprom data memory the attiny26(l) contains 128 bytes of data eeprom memory. it is organized as a sep- arate data space, in which single bytes can be read and written (see ?memory programming? on page 109). the eeprom has an endurance of at least 100,000 write/erase cycles per location. eeprom read/write access the eeprom access registers are accessible in the i/o space. the write access time is typically 8.3 ms. a self-timing function lets the user software detect when the next byte can be written. a special eeprom ready interrupt can be set to trigger when the eeprom is ready to accept new data. an ongoing eeprom write operation will comple te even if a reset condition occurs. in order to prevent unintentional eeprom writes, a two state write procedure must be followed. refer to the description of the eep rom control register for details on this. when the eeprom is written, the cpu is ha lted for two clock cycles before the next instruction is executed. when the eeprom is read, the cpu is halt ed for four clock cycles before the next instruction is executed. eeprom address register ? eear ? bit 7 ? res: reserved bits this bit are reserved bi t in the attiny26(l) and will always read as zero. ? bit 6..0 ? eear6..0: eeprom address the eeprom address register ? eear ? s pecifies the eeprom address in the 128 bytes eeprom space. the eeprom data by tes are addressed lin early between 0 and 127. the initial value of eear is undefined. a prop er value must be written before the eeprom may be accessed. bit 76543210 $1e ($3e) ? eear6 eear5 eear4 eear3 eear2 eear1 eear0 eear read/write r r/w r/w r/w r/w r/w r/w r/w initial value0xxxxxxx 20 attiny26(l) 1477i?avr?10/06 eeprom data register ? eedr ? bit 7..0 ? eedr7..0: eeprom data for the eeprom write operation, the eedr register contains the data to be written to the eeprom in the address gi ven by the eear register. for the eeprom read oper- ation, the eedr contains the data read out from the eeprom at the address given by eear. eeprom control register ? eecr ? bit 7..4 ? res: reserved bits these bits are reserved bits in the attiny26(l) and will always read as zero. ? bit 3 ? eerie: eeprom ready interrupt enable when the i-bit in sreg and eerie are set (one), the eeprom ready interrupt is enabled. when cleared (zero), the interrupt is disabled. the eeprom ready interrupt generates a constant interrupt when eewe is cleared (zero). ? bit 2 ? eemwe: eeprom master write enable the eemwe bit determines w hether setting eewe to one causes the eeprom to be written. when eemwe is set (one), setting eewe will write data to the eeprom at the selected address. if eemwe is zero, setti ng eewe will have no effect. when eemwe has been set (one) by so ftware, hardware clears the bit to zero after four clock cycles. see the description of the eewe bit for an eeprom write procedure. ? bit 1 ? eewe: eeprom write enable the eeprom write enable signal ? eewe ? is the write strobe to the eeprom. when address and data are correctly set up, the eewe bit must be set to write the value in to the eeprom. the eemwe bit must be set wh en the logical one is written to eewe, otherwise no eeprom write takes place. the following procedure should be followed when writing the eeprom (the order of steps 2 and 3 is unessential): 1. wait until eewe becomes zero. 2. write new eeprom addr ess to eear (optional). 3. write new eeprom data to eedr (optional). 4. write a logical one to the eemwe bit in eecr. 5. within four clock cycles after setting eemwe, write a logical one to eewe. caution: an interrupt be tween step 4 and step 5 will make the write cycle fail, since the eeprom master write enable will time-out. if an interrupt routine accessing the eeprom is interrupting an other eeprom access , the eear or eedr register will be modified, causing the interrupted eeprom ac cess to fail. it is recommended to have the global interrupt flag cleared during all the steps to avoid these problems. when the access time (typically 8.3 ms) has elapsed, the eewe bit is cleared (zero) by hardware. the user software c an poll this bit and wait for a zero before writing the next byte. when eewe has been set, the cpu is halted for two cycles before the next instruction is executed. bit 76543210 $1d ($3d) msb lsb eedr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 $1c ($3c) ????eerieeemweeeweeereeecr read/writerrrrr/wr/wr/wr/w initial value00000000 21 attiny26(l) 1477i?avr?10/06 ? bit 0 ? eere: eeprom read enable the eeprom read enable signal ? eere ? is the read strobe to the eeprom. when the correct address is set up in the eear register, the eere bit must be set. when the eere bit is cleared (zero) by hardware, requested data is found in the eedr register. the eeprom read access takes one instruction and there is no need to poll the eere bit. when eere has been set, the cpu is halted for four cycles before the next instruc- tion is executed. the user should poll the eewe bit before starting the read operation. if a write operation is in progress when new data or address is written to the eeprom i/o registers, the write operation will be in terrupted, and the re sult is undefined. note: 1. uses 1 mhz clock, independent of cksel-fuse settings. eeprom write during power- down sleep mode when entering power-down sl eep mode while an eeprom writ e operation is active, the eeprom write operation will cont inue, and will complete before the write access time has passed. however, wh en the write operation is comple ted, the crystal oscillator con- tinues running, and as a consequence, the de vice does not enter power-down entirely. it is therefore recommended to verify that the eeprom write operation is completed before entering power-down. preventing eeprom corruption during periods of low v cc, the eeprom data can be corrupt ed because the supply volt- age is too low for the cpu and the eeprom to operate prope rly. these issues are the same as for board level systems using the eeprom, and the same design solutions should be applied. an eeprom data corruption can be caused by two situations when the voltage is too low. first, a regular write sequence to the eeprom requires a minimum voltage to operate correctly. secondly, the cpu itself ca n execute instructions incorrectly, if the supply voltage for executin g instructions is too low. eeprom data corruption can easily be avoi ded by following thes e design recommen- dations (one is sufficient): 1. keep the avr reset active (low) duri ng periods of insufficient power supply voltage. this can be done by enabling the internal brown-out detector (bod) if the operating voltage matches the detection level. if not, an external brown-out reset protection circuit can be applied. 2. keep the avr core in power-down sleep mode during periods of low v cc . this will prevent the cpu from attempting to decode and execute instructions, effec- tively protecting the eeprom registers from unintentional writes. store constants in flash memory if the abilit y to change memory c ontents from software is not required. flash memory can not be up dated by the cpu, and will not be subject to corruption. table 1. eeprom programming time symbol number of calibrated rc oscillator cycles (1) typical programming time eeprom write (from cpu) 8448 8.5 ms 22 attiny26(l) 1477i?avr?10/06 i/o memory the i/o space definition of the attiny26(l) is shown in table 2 table 2. attiny26(l) i/o space (1) address hex name function $3f ($5f) sreg status register $3d ($5d) sp stack pointer $3b ($5b) gimsk general interrupt mask register $3a ($5a) gifr general interrupt flag register $39 ($59) timsk timer/counter interrupt mask register $38 ($58) tifr timer/counter interrupt flag register $35 ($55) mcucr mcu control register $34 ($54) mcusr mcu status register $33 ($53) tccr0 timer/counter0 control register $32 ($52) tcnt0 timer/counter0 (8-bit) $31 ($51) osccal oscillator calibration register $30 ($50) tccr1a timer/count er1 control register a $2f ($4f) tccr1b timer/count er1 control register b $2e ($4e) tcnt1 timer/counter1 (8-bit) $2d ($4d) ocr1a timer/counter1 output compare register a $2c ($4c) ocr1b timer/counter1 output compare register b $2b ($4b) ocr1c timer/counter1 output compare register c $29 ($29) pllcsr pll control and status register $21 ($41) wdtcr watchdog timer control register $1e ($3e) eear eeprom address register $1d ($3d) eedr eeprom data register $1c ($3c) eecr eeprom control register $1b ($3b) porta data register, port a $1a ($3a) ddra data direction register, port a $19 ($39) pina input pins, port a $18 ($38) portb data register, port b $17 ($37) ddrb data direction register, port b $16 ($36) pinb input pins, port b $0f ($2f) usidr universal serial interface data register $0e ($2e) usisr universal serial interface status register $0d ($2d) usicr universal serial interface control register $08 ($28) acsr analog comparator control and status register $07 ($27) admux adc multiplexer select register 23 attiny26(l) 1477i?avr?10/06 note: 1. reserved and unused locations are not shown in the table. all attiny26(l) i/o and peripheral registers are placed in the i/o space. the i/o loca- tions are accessed by the in and out instructions transferring data between the 32 general purpose working registers and the i/o space. i/o registers within the address range $00 - $1f are directly bit-accessible using the sbi and cbi instructions. in these registers, the value of single bits can be checked by using the sbis and sbic instruc- tions. refer to the in struction set chap ter for more details. for compatibility with future devices, reserved bits should be written zero if accessed. reserved i/o memory addresses should never be written. $06($26) adcsr adc control and status register $05($25) adch adc data register high $04($24) adcl adc data register low table 2. attiny26(l) i/o space (1) (continued) address hex name function 24 attiny26(l) 1477i?avr?10/06 system clock and clock options clock systems and their distribution figure 20 presents the principal clock system s in the avr and their distribution. all of the clocks need not be active at a given time. in order to reduce power consumption, the clocks to modules not being used can be halted by using differ ent sleep modes, as described in ?power management and sleep modes? on page 38. the clock systems are detailed below. figure 20. clock distribution cpu clock ? clk cpu the cpu clock is routed to parts of the system concerned with operation of the avr core. examples of such modules are the general purpose register file, the status reg- ister and the data memory holding the stack pointer. halting the cpu clock inhibits the core from performing general operations and calculations. i/o clock ? clk i/o the i/o clock is used by the majority of the i/o modules, like timer/counters, and usi. the i/o clock is also used by the external interrupt module, but note that some external interrupts are detected by asynchronous logic, allowing such interrupts to be detected even if the i/o clock is halted. flash clock ? clk flash the flash clock controls operation of the fl ash interface. the flash clock is usually active simultaneously with the cpu clock. adc clock ? clk adc the adc is provided with a dedicated clock domain. this allows halting the cpu and i/o clocks in order to reduce noise generated by digital circuitry. this gives more accu- rate adc conversion results. general i/o modules timer/counter1 adc cpu core ram clk i/o avr clock control unit clk cpu flash and eeprom clk flash clk adc source clock watchdog timer watchdog oscillator reset logic clock multiplexer watchdog clock calibrated rc oscillator pll crystal oscillator low-frequency crystal oscillator external rc oscillator clk pll clk pck external clock 25 attiny26(l) 1477i?avr?10/06 internal pll for fast peripheral clock generation ? clk pck the internal pll in attiny26(l) generates a clock frequency that is 64x multiplied from nominally 1 mhz input. the source of the 1 mhz pll input clock is the output of the internal rc oscillator which is automatically divided down to 1 mhz, if needed. see the figure 21 on page 25. when the pll reference frequency is the nominal 1 mhz, the fast peripheral clock is 64 mhz. the fast peripheral clock, or a clock prescaled from that, can be selected as the clock source for timer/counter1. the pll is locked on the rc oscillator and adjusting the rc oscillator via osccal register will adjust the fast peripheral clock at the same time. howe ver, even if the pos- sibly divided rc oscillator is taken to a hig her frequency than 1 mh z, the fast peripheral clock frequency saturates at 70 mhz (worst case) and remain s oscillating at the maxi- mum frequency. it should be noted that the pll in this case is not locked any more with the rc oscillator clock. therefore it is recommended not to take the osccal adjustments to a higher fre- quency than 1 mhz in order to keep the pll in the correct operating range. the internal pll is enabled only when the plle bit in the register pllcsr is set or the pllck fuse is programmed (?0?). the bit plock from the register pllcsr is set when pll is locked. both internal 1 mhz rc oscillator and pll are switched off in po wer-down and standby sleep modes. figure 21. pck clocking system 1 2 4 8 mhz rc oscillator osccal xtal1 xtal2 oscillators divide to 1 mhz divide by 4 ck pll 64x pllck & cksel fuses plle pck lock detector plock 26 attiny26(l) 1477i?avr?10/06 clock sources the device has the following clock source options, selectable by flash fuse bits as shown below on table 3. the clock from the selected source is input to the avr clock generator, and routed to the appropriate modules.the use of pins pb5 (xtal2), and pb4 (xtal1) as i/o pins is limited depending on clock settings, as shown below in table 4. note: 1. for all fuses ?1? means unprogrammed while ?0? means programmed. the various choices for each clocking option is given in the followi ng sections. when the cpu wakes up from power-down, the selected clock source is used to time the start-up, ensuring stable oscillator operation before instruction execution starts. when the cpu starts from reset, there is as an additional delay allowing the power to reach a stable level before commencing normal operation. the watchdog oscillator is used for timing this real-time part of the st art-up time. the number of wd t oscillator cycles used for table 3. device clocking options select device clocking op tion pllck cksel3..0 external crystal/ceramic resonator 1 1111 - 1010 external low-frequency crystal 1 1001 external rc oscillator 1 1000 - 0101 calibrated internal rc oscillator 1 0100 - 0001 external clock 1 0000 pll clock 0 0001 table 4. pb5, and pb4 functionality vs. device clocking options (1) device clocking option pllck cksel [3:0] pb4 pb5 external clock 1 0000 xtal1 i/o internal rc oscillator 1 0001 i/o i/o internal rc oscillator 1 0010 i/o i/o internal rc oscillator 1 0011 i/o i/o internal rc oscillator 1 0100 i/o i/o external rc oscillator 1 0101 xtal1 i/o external rc oscillator 1 0110 xtal1 i/o external rc oscillator 1 0111 xtal1 i/o external rc oscillator 1 1000 xtal1 i/o external low-frequency oscillator 1 1001 xtal1 xtal2 external crystal/resonator oscillator 1 1010 xtal1 xtal2 external crystal/resonator oscillator 1 1011 xtal1 xtal2 external crystal/resonator oscillator 1 1100 xtal1 xtal2 external crystal/resonator oscillator 1 1101 xtal1 xtal2 external crystal/resonator oscillator 1 1110 xtal1 xtal2 external crystal/resonator oscillator 1 1111 xtal1 xtal2 pll 0 0001 i/o i/o 27 attiny26(l) 1477i?avr?10/06 each time-out is shown in table 5. the fr equency of the watchdog oscillator is voltage dependent as shown in the electrical characteristics section. default clock source the deviced is shipped with cksel = ?0001?, sut = ?10?, and pllck unprogrammed. the default clock source settin g is therefore the internal rc oscillator with longest star- tup time. this default setting ensures that all users can make their desired clock source setting using an in-system or parallel programmer. crystal oscillator xtal1 and xtal2 are input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillato r, as shown in figure 22. either a quartz crystal or a ceramic resonator may be used. the maximum frequency for resonators is 12 mhz. the ckopt fuse should always be unprogrammed when using this clock option. c1 and c2 should always be equal. the optimal value of the capacitors depends on the crystal or resonator in use, the amount of stray capacitance, and the electromag- netic noise of the environment. some initia l guidelines for choosing capacitors for use with crystals are given in table 6. for ceramic resonators, the capacitor values given by the manufacturer should be used. figure 22. crystal oscillator connections the oscillator can operate in three different modes, each optimized for a specific fre- quency range. the operating mode is selected by the fuses cksel3..1 as shown in table 6. note: 1. this option should not be used with crystals, only with ceramic resonators. table 5. number of watchdog oscillator cycles typ time-out (v cc = 5.0v) typ time-out (v cc = 3.0v) number of cycles 4.1 ms 4.3 ms 4k (4,096) 65 ms 69 ms 64k (65,536) table 6. crystal oscillator operating modes cksel3..1 frequency range (mhz) recommended range for capacitors c1 and c2 for use with crystals (pf) 101 (1) 0.4 - 0.9 ? 110 0.9 - 3.0 12 - 22 111 3.0 - 16 12 - 22 16 - 12 - 15 xtal2 xtal1 gnd c2 c1 28 attiny26(l) 1477i?avr?10/06 the cksel0 fuse together with the sut1..0 fuses select the start-up times as shown in table 7. notes: 1. these options should only be used wh en not operating close to the maximum fre- quency of the device, and only if frequency stabili ty at start-up is not important for the application. 2. these options are intended for use with ceramic resonators and will ensure fre- quency stability at start-up. they can also be used with crystals when not operating close to the maximum frequency of the device, and if frequency stability at start-up is not important for the application. low-frequency crystal oscillator to use a 32.768 khz watch crystal as the clock source for the device, the low-fre- quency crystal oscillator must be selected by setting the pllck to ?1? and cksel fuses to ?1001?. the crystal should be connected as shown in figure 22. by program- ming the ckopt fuse, the user can enable internal capacitors on xtal1 and xtal2, thereby removing the need for external capacito rs. the internal capacitors have a nomi- nal value of 36 pf. when this oscillator is sele cted, start-up times are dete rmined by the sut fuses as shown in table 8. note: 1. these options should only be used if frequ ency stability at start-up is not important for the application. table 7. start-up times for the crystal oscillator clock selection cksel0 sut1..0 start-up time from power-down additional delay from reset (v cc = 5.0v) recommended usage 0 00 258 ck (1) 4.1 ms ceramic resonator, fast rising power 0 01 258 ck (1) 65 ms ceramic resonator, slowly rising power 010 1k ck (2) ? ceramic resonator, bod enabled 011 1k ck (2) 4.1 ms ceramic resonator, fast rising power 100 1k ck (2) 65 ms ceramic resonator, slowly rising power 1 01 16k ck ? crystal oscillator, bod enabled 1 10 16k ck 4.1 ms crystal oscillator, fast rising power 1 11 16k ck 65 ms crystal oscillator, slowly rising power table 8. start-up times for the lo w-frequency crystal os cillator clock selection sut1..0 start-up time from power-down additional delay from reset (v cc = 5.0v) recommended usage 00 1k ck (1) 4.1 ms fast rising power or bod enabled 01 1k ck (1) 65 ms slowly rising power 10 32k ck 65 ms stable frequency at start-up 11 reserved 29 attiny26(l) 1477i?avr?10/06 external rc oscillator for timing insensitive applications, the exte rnal rc configuration shown in figure 23 can be used. the frequency is roughly estima ted by the equation f = 1/(3rc). c should be at least 22 pf. by programming the ckopt fuse, the user can enable an internal 36 pf capacitor between xtal1 and gnd, thereby removing the need for an external capacitor. figure 23. external rc configuration the oscillator can operate in four different modes, each optimized for a specific fre- quency range. the operating mode is selected by the fuses cksel3..0 as shown in table 9. when this oscillator is sele cted, start-up times are dete rmined by the sut fuses as shown in table 10. notes: 1. this option should not be used when operating close to the maximum frequency of the device. table 9. external rc oscilla tor operating modes cksel3..0 frequency range (mhz) 0101 0.1 - 0.9 0110 0.9 - 3.0 0111 3.0 - 8.0 1000 8.0 - 12.0 table 10. start-up times for the external rc oscillator clock selection sut1..0 start-up time from power-down additional delay from reset (v cc = 5.0v) recommended usage 00 18 ck ? bod enabled 01 18 ck 4.1 ms fast rising power 10 18 ck 65 ms slowly rising power 11 6 ck (1) 4.1 ms fast rising power or bod enabled pb5 (xtal2) xtal1 gnd v cc r c 30 attiny26(l) 1477i?avr?10/06 calibrated internal rc oscillator the calibrated internal rc oscillator provides a fixed 1.0, 2.0, 4.0, or 8.0 mhz clock. all frequencies are nominal values at 5v and 25 c. this clock may be selected as the sys- tem clock by programming the cksel fuses as shown in table 11. if selected, it will operate with no external components. the ckopt fuse should always be unpro- grammed when using this clock option. duri ng reset, hardware loads the calibration byte into the osccal register and thereb y automatically calibra tes the rc oscillator. at 5v, 25 c and 1.0 mhz oscillator frequency se lected, this calibration gives a fre- quency within 3% of the nominal frequency. using run-time calibration methods as described in application notes available at www.atmel.com/avr it is possible to achieve 1% accuracy at any given v cc and temperature. when this oscillator is used as the chip clock, the watchdog oscillator will still be us ed for the watchdog ti mer and for the reset time-out. for more information on the pre-programmed calibration value, see the section ?calibration byte? on page 111. note: 1. the device is shipped with this option selected. when this oscillator is sele cted, start-up times are dete rmined by the sut fuses as shown in table 12. pb4 (xtal1) and pb5 (xtal2) can be used as general i/o ports. note: 1. the device is shipped with this option selected. oscillator calibration register ? osccal ? bits 7..0 ? cal7..0: oscillator calibration value writing the calibration byte to this address will trim the inte rnal oscillator to remove pro- cess variations from the osc illator frequency. duri ng reset, the 1 mh z calibration value which is located in the signature row high byte (address 0x00) is automatically loaded into the osccal register. if the internal rc is used at other frequencies, the calibration value must be loaded manually. this can be done by first reading the signature row by a programmer, and then store the calibration values in the flash or eeprom. then the value can be read by software and loaded into the osccal register. when osccal is zero, the lowest available frequency is chosen. writing non-zero values to this register table 11. internal calibrated rc os cillator oper ating modes cksel3..0 nominal frequency (mhz) 0001 (1) 1.0 0010 2.0 0011 4.0 0100 8.0 table 12. start-up times for the internal cali brated rc oscillator clock selection sut1..0 start-up time from power-down additional delay from reset (v cc = 5.0v) recommended usage 00 6 ck ? bod enabled 01 6 ck 4.1 ms fast rising power 10 (1) 6 ck 65 ms slowly rising power 11 reserved bit 76543210 $31 ($51) cal7 cal6 cal5 cal4 cal3 cal2 cal1 cal0 osccal read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value device spec ific calibration value 31 attiny26(l) 1477i?avr?10/06 will increase the frequency of the internal oscilla tor. writing $ff to th e register gives the highest available frequency. the calibrated os cillator is used to time eeprom and flash access. if eeprom or flas h is written, do not calibr ate to more than 10% above the nominal frequency. otherwise, the eeprom or flash write may fail. note that the oscillator is intended for calibrati on to 1.0, 2.0, 4.0, or 8.0 m hz. tuning to other values is not guaranteed, as indicated in table 13. external clock to drive the device from an external clock source, xtal1 should be driven as shown in figure 24. to run the device on an extern al clock, the cksel fuses must be pro- grammed to ?0000? and pllck to ?1?. by programming the ckopt fuse, the user can enable an internal 36 pf capacitor between xtal1 and gnd. figure 24. external clock drive configuration when this clock source is selected, start- up times are determined by the sut fuses as shown in table 14. when applying an external clock, it is required to avoid sudden changes in the applied clock frequency to ensure stable operation of the mcu. a variation in frequency of more than 2% from one clock cycle to the nex t can lead to unpredictable behaviour. it is required to ensure that the mcu is kept in reset during such changes in the clock frequency. table 13. internal rc oscillator frequency range. osccal value min frequency in percentage of nominal frequency max frequency in percentage of nominal frequency $00 50% 100% $7f 75% 150% $ff 100% 200% table 14. start-up times for the external clock selection sut1..0 start-up time from power-down additional delay from reset (v cc = 5.0v) recommended usage 00 6 ck ? bod enabled 01 6 ck 4.1 ms fast rising power 10 6 ck 65 ms slowly rising power 11 reserved external clock signal pb5 (xtal2) xtal1 gnd 32 attiny26(l) 1477i?avr?10/06 high frequency pll clock ? pll clk there is an internal pll that provides nom inally 64 mhz clock rate locked to the rc oscillator for the use of the peripheral timer/counter1 and for the system clock source. when selected as a system clock source, by programming (?0?) the fuse pllck, it is divided by four. when this option is used, the cksel3..0 must be set to ?0001?. this clocking option can be used only when operating between 4.5 - 5.5v to guaratee safe operation. the system clock frequency will be 16 mhz (64 mhz/4). when using this clock option, start-up times are determined by the sut fuses as shown in table 15. see also ?pck clocking system? on page 25. table 15. start-up times for the pllck sut1..0 start-up time from power-down additional delay from reset (v cc = 5.0v) recommended usage 00 1k ck ? bod enabled 01 1k ck 4.1 ms fast rising power 10 1k ck 65 ms slowly rising power 11 16k ck ? slowly rising power 33 attiny26(l) 1477i?avr?10/06 system control and reset the attiny26(l) provides four sources of reset: ? power-on reset. the mcu is reset when the supply voltage is below the power-on reset threshold (v pot ). ? external reset. to use the pb7/reset pin as an external reset , instead of i/o pin, unprogram (?1?) the rstdisbl fuse. the mcu is reset when a low level is present on the reset pin for more than 500 ns. ? watchdog reset. the mcu is reset when the watchdog timer period expires and the watchdog is enabled. ? brown-out reset. the mcu is reset when the supply voltage v cc is below the brown-out reset threshold (v bot ). during reset, all i/o registers are then set to their initial values, and the program starts execution from address $000. the instructio n placed in address $000 must be an rjmp ? relative jump ? instruction to the reset handling routine. if the program never enables an interrupt source, the interrupt vectors are not used, and regular program code can be placed at these locations. figure 25 shows the reset logic for the attiny26(l). table 16 shows the timing and electrical parameters of the reset circuitry for attiny26(l). figure 25. reset logic for the attiny26(l) mcu status register (mcusr) brown-out reset circuit boden bodlevel delay counters cksel[3:0] ck timeout wdrf borf extrf porf data b u s clock generator 34 attiny26(l) 1477i?avr?10/06 notes: 1. the power-on reset will not work unless the supply voltage has been below v pot (falling) 2. v bot may be below nominal minimum operating voltage for some devices. for devices where this is the case, t he device is tested down to v cc = v bot during the production test. this guarantees that a brown-out reset will occur before v cc drops to a voltage where correct operation of the microcontroller is no longer guaranteed. the test is performed using bodlevel=1 for attiny26l and bodlevel=0 for attiny26. bodlevel=1 is not applicable for attiny26. see start-up times from reset from ?system clock and clock options? on page 24. when the cpu wakes up from power-down, only the clock counting part of the start-up time is used. the watchdog oscillator is used for timing the real-time part of th e start-up time. power-on reset a power-on reset (por) pulse is generated by an on-chip detection circuit. the detec- tion level is defined in table 16 the por is activated whenever v cc is below the detection level. the por circuit can be used to trigger the start-up reset, as well as detect a failure in supply voltage. the power-on reset (por) circuit ensures t hat the device is reset from power-on. reaching the power-on reset threshold voltage invokes a delay counter, which deter- mines the delay, for which the device is kept in reset after v cc rise. the time-out period of the delay counter can be defined by the user through the cksel fuses. the different selections for the delay period are presented in ?system clock and clock options? on page 24. the reset signal is activated again, without any delay, when the v cc decreases below detection level. table 16. reset characteristics symbol parameter condition min typ max units v pot power-on reset threshold voltage (rising) 1.4 2.3 v power-on reset threshold voltage (falling) (1) 1.3 2.3 v v rst reset pin threshold voltage 0.2 0.9 v cc t rst minimum pulse width on reset pin 1.5 s v bot brown-out reset threshold voltage (2) bodlevel = 1 2.4 2.7 2.9 v bodlevel = 0 3.7 4.0 4.5 t bod minimum low voltage period for brown-out detection bodlevel = 1 2 s bodlevel = 0 2 s v hyst brown-out detector hysteresis 130 mv 35 attiny26(l) 1477i?avr?10/06 figure 26. mcu start-up, reset tied to vcc figure 27. mcu start-up, reset controlled externally external reset an external reset is generated by a low level on the reset pin. reset pulses longer than 500 ns will gener ate a reset, even if the clock is not running. shorter pulses are not guaranteed to generate a reset. when the applied signal reaches the reset threshold voltage ? v rst ? on its positive edge, the delay timer starts the mcu after the time-out period t tout has expired. figure 28. external reset during operation vcc reset time-out internal reset t tout v pot v rst vcc reset time-out internal reset t tout v pot v rst vcc reset time-out internal reset t tout v rst 36 attiny26(l) 1477i?avr?10/06 brown-out detection attiny26(l) has an on-chip brown-out detection (bod) circuit for monitoring the v cc level during the operation. the bod circuit can be enabled/disabled by the fuse boden. when the bod is enabled (boden programmed), and v cc decreases below the trigger level, the brown-out reset is immediately activated. when v cc increases above the trigger level, the brown-out rese t is deactivated after a delay. the delay is defined by the user in the same way as the delay of por signal, in table 29. the trigger level for the bod can be selected by the fuse bodlevel to be 2.7v (bodlevel unprogrammed), or 4.0v (bodlevel programmed). the trigger level has a hysteresis of 50 mv to ensure spike free brown-out detection. the bod circuit will only detect a drop in v cc if the voltage stays below the trigger level for longer than t bod given in table 16. figure 29. brown-out reset during operation watchdog reset when the watchdog times out, it will generate a short rese t pulse of one ck cycle dura- tion. on the falling edge of this pulse, the delay timer starts counting the time-out period t tout . refer to page 80 for details on operation of the watchdog. figure 30. watchdog time-out v cc reset time-out internal reset v bot- v bot+ t tout 1 ck cycle 37 attiny26(l) 1477i?avr?10/06 mcu status register ? mcusr ? bit 7..4 ? res: reserved bits these bits are reserved bits in the attiny26(l) and always read as zero. ? bit 3 ? wdrf: watchdog reset flag this bit is set (one) if a watchdog reset occurs. the bit is reset (zero) by a power-on reset, or by writing a logic zero to the flag. ? bit 2 ? borf: brown-out reset flag this bit is set (one) if a brown-out reset occurs. the bit is reset (zero) by a power-on reset, or by writing a logic zero to the flag. ? bit 1 ? extrf: external reset flag this bit is set (one) if an external reset occurs. the bit is reset (zero) by a power-on reset, or by writing a logic zero to the flag. ? bit 0 ? porf: power-on reset flag this bit is set (one) if a power-on reset occurs. the bit is reset (zero) by writing a logic zero to the flag. to make use of the reset flags to identify a reset condition, the user should read and then reset (zero) the mcusr as early as possible in the program. if the register is cleared before another reset occurs, the source of the reset can be found by examining the reset flags. bit 76543210 $34 ($54) ????wdrfborfextrfporfmcusr read/write r r r r r/w r/w r/w r/w initial value0000 see bit description 38 attiny26(l) 1477i?avr?10/06 power management and sleep modes sleep modes enable the application to shut down unused modules in the mcu, thereby saving power. the avr provides various sleep modes allowing the user to tailor the power consumption to the application?s requirements. to enter any of the four sleep modes, the se bit in mcucr must be written to logic one and a sleep instruction must be executed. the sm1, and sm0 bits in the mcucr register select which sleep mode (idle, adc noise reduction, power down, or stand- by) will be activated by the sleep instruct ion. see table 17 fo r a summary. if an enabled interrupt occurs while the mcu is in a sleep mode, the mcu wakes up. the mcu is then halted for four cycles in addition to the start-up time, it executes the inter- rupt routine, and resumes ex ecution from the in struction following sleep. the contents of the register file and sram are unaltered when the device wakes up from sleep. if a reset occurs during sleep mode, the mcu wakes up and executes from the reset vector. table 19 on page 40 presents the different clock systems in the attiny26, and their dis- tribution. the figure is helpful in selecting an appropriate sleep mode. mcu control register ? mcucr the mcu control register contains control bits for general mcu functions. ? bits 7 ? res: reserved bit this bit is a reserved bit in the attiny26(l) and always reads as zero. ? bit 6 ? pud: pull-up disable when this bit is set (one), the pull-ups in the i/o ports are disabled even if the ddxn and portxn registers are configured to enable the pull-ups ({ddxn, portxn} = 0b01). see ?configuring the pin? on page 44 for more details about this feature. ? bit 5 ? se: sleep enable the se bit must be set (one) to make the mcu enter the sleep mode when the sleep instruction is executed. to avoid the mcu entering the sleep mode unless it is the pro- grammers purpose, it is recommended to set the sleep enable se bit just before the execution of the sleep instruction. ? bits 4,3 ? sm1/sm0: sleep mode select bits 1 and 0 these bits select between the four available sleep modes, as shown in the following table. for details, refer to the paragraph ?sleep modes? below. ? bit 2 ? res: reserved bit this bit is a reserved bit in the attiny26(l) and always reads as zero. bit 76543210 $35 ($55) ? pud se sm1 sm0 ? isc01 isc00 mcucr read/write r r/w r/w r/w r/w r r/w r/w initial value00000000 table 17. sleep modes sm1 sm0 sleep mode 0 0 idle mode 0 1 adc noise reduction mode 1 0 power-down mode 1 1 standby mode 39 attiny26(l) 1477i?avr?10/06 ? bits 1, 0 ? isc01, isc00: interrupt sense control 0 bit 1 and bit 0 the external interrupt 0 is activated by the external pin int0 if the sreg i-flag and the corresponding interrupt mask is set (one). the activity on the external int0 pin that acti- vates the interrupt is defined in the following table. note: 1. when changing the isc10/isc00 bits, int0 must be disabled by clearing its interrupt enable bit in the gimsk register. otherwise an interrupt can occur when the bits are changed. idle mode when the sm1..0 bits are written to ?00?, the sleep in struction makes the mcu enter idle mode, stopping the cpu but allowing analog comparator, adc, usi, timer/counters, watchdog, and the interrupt system to continue operating. this sleep mode basically halts clk cpu and clk flash , while allowing the ot her clocks to run. idle mode enables the mcu to wake up fr om external triggered interrupts as well as internal ones like the timer overflow and us i start and overflow interrupts. if wake-up from the analog comparator interrupt is not required, the analog comparator can be powered down by setting the acd bit in the analog comparator control and status register ? acsr. this will reduce power co nsumption in idle mode. if the adc is enabled, a conversion starts automatically when this mode is entered. adc noise reduction mode when the sm1..0 bits are written to ?01?, the sleep in struction makes the mcu enter adc noise reduction mode, stopping the cpu but allowing the adc, the external inter- rupts, the usi start condition detection, and the watchdog to continue operating (if enabled). this sleep mode basically halts clk i/o , clk cpu , and clk flash , while allowing the other clocks to run. this improves the noise environment for the adc, enabling higher resolution measure- ments. if the adc is enabled, a conversion starts automatically when this mode is entered. apart form the adc conversion complete interrupt, only an external reset, a watchdog reset, a brown-out reset, usi start condition interrupt, an eeprom ready interrupt, an external level interrupt on int0, or a pin change interrupt can wake up the mcu from adc noise reduction mode. power-down mode when the sm1..0 bits are written to ?10?, the sleep in struction makes the mcu enter power-down mode. in this mode, the external oscillator is stopped, while the external interrupts, the usi start condition detec tion, and the watchdog continue operating (if enabled). only an external reset, a watchdog reset, a brown-out reset, usi start con- dition interrupt, an external level interrupt on int0, or a pin change interrupt can wake up the mcu. this sleep mode basically halts all generated clocks, allowing operation of asynchronous modules only. when waking up from power-down mode, there is a delay from the wake-up condition occurs until the wake-up becomes effective. this allows the clock to restart and become stable after having been stopped. the wake-up period is defined by the same cksel fuses that define the reset time-out period, as described in ?clock sources? on page 26. table 18. interrupt 0 sense control (1) isc01 isc00 description 0 0 the low level of int0 generates an interrupt request. 0 1 any change on int0 generates an interrupt request. 1 0 the falling edge of int0 generates an interrupt request. 1 1 the rising edge of int0 generates an interrupt request. 40 attiny26(l) 1477i?avr?10/06 note that if a level triggered external interrupt or pin change interrupt is used from power-down mode, the changed level must be held for some time to wake up the mcu. this makes the mcu less sensitive to noise. if the wake-up condition disappears before the mcu wakes up and starts to execute, e.g., a low level on int0 is not held long enough, the interrupt causing the wake-up will not be executed. standby mode when the sm1..0 bits are ?11? and an ex ternal crystal/resonator clock option is selected, the sleep instruction forces t he mcu into the standby mode. this mode is identical to power-down with the exception that the oscillator is kept running. from standby mode, the device wakes up in only six clock cycles. notes: 1. only recommended with external crystal or resonator selected as clock source. 2. only level interrupt int0. table 19. active clock domains and wake-up sources in the different sleep modes. active clock domains oscillators wake-up sources sleep mode clk cpu clk flash clk io clk adc main clock source enabled int0, and pin change usi start condition eeprom ready adc other i/o idle x x x x x x x x adc noise reduction x x x (2) xxx power-down x (2) x standby (1) xx (2) x 41 attiny26(l) 1477i?avr?10/06 minimizing power consumption there are several issues to consider when trying to minimize the power consumption in an avr controlled system. in general, sleep modes should be used as much as possi- ble, and the sleep mode should be selected so that as few as pos sible of the device?s functions are operating. all functions not needed should be disabled. in particular, the following modules may need special consider ation when trying to achieve the lowest possible power consumption. analog to digital converter if enabled, the adc will be enabled in all sleep modes. to save power, the adc should be disabled before entering any sleep mode. when the adc is turned off and on again, the next conversion will be an extended conversion. refer to ?analog to digital con- verter? on page 96 for details on adc operation. analog comparator when entering idle mode, the analog comparator should be disabled if not used. when entering adc noise reduction mode, the analog comparator should be disabled. in the other sleep modes, the analog comparator is automatically disabled. however, if the analog comparator is set up to use the internal voltage reference as input, the analog comparator should be disabled in all sleep modes. otherwise, the internal voltage ref- erence will be enabled, independent of sleep mode. refer to ?analog comparator? on page 93 for details on how to configure the analog comparator. brown-out detector if the brown-out detector is not needed in the application, this module should be turned off. if the brown-out detector is enabled by the boden fuse, it will be enabled in all sleep modes, and hence, always consume power. in the deeper sleep modes, this will contribute significantly to the total current consumption. refer to ?brown-out detection? on page 36 for details on how to configure the brown-out detector. internal voltage reference the internal voltage reference (see table 20) will be enabled when needed by the brown-out detector, the analog comparator or the adc. if these modules are disabled as described in the sections above, the in ternal voltage reference will be disabled and it will not be consuming power. w hen turned on again, the us er must allow the reference to start up before the output is used. if the reference is kept on in sleep mode, the output can be used immediately. watchdog timer if the watchdog timer is not needed in the application, this module should be turned off. if the watchdog timer is enabled, it will be enabled in all sleep modes, and hence, always consume power. in the deeper sleep modes, this will contribute significantly to the total current consumption. refer to ?watchdog timer? on page 80 for details on how to configure the watchdog timer. port pins when entering a sleep mode, all port pins should be configured to use minimum power. the most important thing is then to ensure that no pins drive resistive loads. in sleep modes where the both the i/o clock (clk i/o ) and the adc clock (clk adc ) are stopped, the input buffers of the de vice will be disabled. this ensure s that no power is consumed by the input logic when not needed. in some cases, the input logic is needed for detecting wake-up conditions, and it will th en be enabled. refer to ? digital input en able and sleep modes? on page 47 for details on which pins are enabled. if the input buffer is enabled table 20. internal voltage reference symbol parameter min typ max units v bg bandgap reference voltage 1.15 1.18 1.40 v t bg bandgap reference start-up time 40 70 s i bg bandgap reference current consumption 10 a 42 attiny26(l) 1477i?avr?10/06 and the input signal is left floating or have an analog signal level close to v cc /2, the input buffer will use excessive power. 43 attiny26(l) 1477i?avr?10/06 i/o ports introduction all avr ports have true read-modify-write functionality when used as general digital i/o ports. this means that the direction of one port pin can be changed without uninten- tionally changing the direction of any other pin with the sbi and cbi instructions. the same applies when changing drive value (if c onfigured as output) or enabling/disabling of pull-up resistors (if configured as input). each output buffer, except reset, has sym- metrical drive characte ristics with both high si nk and source capability. the pin driver is strong enough to drive led displays directly. all port pins have individually selectable pull-up resistors with a supply-voltage inva riant resistance. all i/o pins have protection diodes to both v cc and ground as indicated in figure 31. figure 31. i/o pin equivalent schematic all registers and bit references in this section are written in general form. a lower case ?x? represents the numbering letter for the port, and a lower case ?n? represents the bit number. however, when using the register or bit defines in a program, the precise form must be used. for example, portb3 for bit no. 3 in port b, here documented generally as portxn. the physical i/o registers and bit locations are listed in ?register descrip- tion for i/o ports? on page 58. three i/o memory address locations are allocated for each port, one each for the data register ? portx, data direction register ? ddrx, and the port input pins ? pinx. the port input pins i/o location is read only, while the data register and the data direction register are read/write. in addition, the pull-up disable ? pud bit in mcucr disables the pull-up function for all pins in all ports when set. using the i/o port as general dig ital i/o is described in ?ports as general digital i/o? on page 44. most port pins are multiplexed with alternate functions for the peripheral fea- tures on the device. how each alternate function interferes with the port pin is described in ?alternate port functions? on page 48. refer to the individual module sections for a full description of the alternate functions. note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as general digital i/o. c pin logic r pu see figure "general digital i/o" fo r details pxn 44 attiny26(l) 1477i?avr?10/06 ports as general digital i/o the ports are bi-directional i/o ports with optional internal pull-ups. figure 32 shows a functional description of one i/o-port pin, here generically called pxn. figure 32. general digital i/o (1) note: 1. wpx, wdx, rrx, rpx, and rdx are common to all pins within the same port. clk i/o , sleep, and pud are common to all ports. configuring the pin each port pin consists of 3 register bits: ddxn, portxn, and pinxn. as shown in ?reg- ister description for i/o ports? on page 58, th e ddxn bits are accessed at the ddrx i/o address, the portxn bits at the portx i/o address, and the pinxn bits at the pinx i/o address. the ddxn bit in the ddrx register selects the direction of this pin. if ddxn is written logic one, pxn is configured as an output pin. if ddxn is written logic zero, pxn is config- ured as an input pin. if portxn is written logic one when the pin is configured as an input pin, the pull-up resistor is activated. to switch the pull-up resistor off, portxn has to be written logic zero or the pin has to be configured as an output pin. the port pins are tri-stated when a reset condition becomes active, even if no clocks are running. if portxn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). if portxn is written logic zero when the pin is configured as an out- put pin, the port pin is driven low (zero). when switching between tri-state ({ddxn, portxn} = 0b00) and output high ({ddxn, portxn} = 0b11), an intermediate state with either pull-up enabled ({ddxn, portxn} = 0b01) or output low ({ddxn, portxn} = 0b10) must occur. normally, the pull-up enabled state is fully accept able, as a high-impedant envi ronment will not notice the clk rpx rrx wpx rdx wdx pud synchronizer wdx: write ddrx wpx: write portx rrx: read portx register rpx: read portx pin pud: pullup disable clk i/o : i/o clock rdx: read ddrx d l q q reset reset q q d q q d clr portxn q q d clr ddxn pinxn data b u s sleep sleep: sleep control pxn i/o 45 attiny26(l) 1477i?avr?10/06 difference between a strong high driver and a pull-up. if this is not the case, the pud bit in the mcucr register can be set to disable all pull-ups in all ports. switching between input with pull-up and output low generates the same problem. the user must use either the tri-state ({ddxn, portxn} = 0b00) or the output high state ({ddxn, portxn} = 0b11) as an intermediate step. table 21 summarizes the control signals for the pin value. reading the pin value independent of the setting of data direction bit ddxn, the port pin can be read through the pinxn register bit. as shown in figure 32, the pinxn register bit and the preceding latch constitute a synchronizer. this is needed to avoid metastability if the physical pin changes value near the edge of the internal cl ock, but it also introduces a delay. figure 33 shows a timing diagram of the synchroni zation when reading an externally applied pin value. the maximum and minimum propagation delays are denoted t pd,max and t pd,min respectively. figure 33. synchronization when reading an externally applied pin value consider the clock period starting shortly after the first falling edge of the system clock. the latch is closed when the clock is low, and goes transparent when the clock is high, as indicated by the shaded region of t he ?sync latch? signal. the signal value is latched when the system clock goes low. it is clocked into the pinxn register at the suc- ceeding positive clock edge. as indicated by the two arrows t pd,max and t pd,min , a single table 21. port pin configurations ddxn portxn pud (in mcucr) i/o pull-up comment 0 0 x input no tri-state (hi-z) 0 1 0 input yes pxn will source current if ext. pulled low 0 1 1 input no tri-state (hi-z) 1 0 x output no output low (sink) 1 1 x output no output high (source) xxx in r17, pinx 0x00 0xff instructions sync latch pinxn r17 xxx system clk t pd, max t pd, min 46 attiny26(l) 1477i?avr?10/06 signal transition on the pin will be delay ed between ? and 1? system clock period depending upon the time of assertion. when reading back a software assigned pin value, a nop instruction must be inserted as indicated in figure 34. the out instruction sets the ?sync latch? signal at the positive edge of the clock. in this case, the delay t pd through the synchronizer is one system clock period. figure 34. synchronization when reading a software assigned pin value out portx, r16 nop in r17, pinx 0xff 0x00 0xff system clk r16 instructions sync latch pinxn r17 t pd 47 attiny26(l) 1477i?avr?10/06 the following code example shows how to set port b pins 0 and 1 high, 2 and 3 low, and define the port pins from 4 to 7 as input with pull-ups assigned to port pins 6 and 7. the resulting pin values are read back again, but as previously discussed, a nop instruction is included to be able to read back the value recently assigned to some of the pins. note: 1. for the assembly program, two tempor ary registers are used to minimize the time from pull-ups are set on pins 0, 1, 6, and 7, until the direction bits are correctly set, defining bit 2 and 3 as low and redefini ng bits 0 and 1 as strong high drivers. digital input enable and sleep modes as shown in figure 32, the digital input si gnal can be clamped to ground at the input of the schmitt-trigger. the signal denoted sleep in the figure, is set by the mcu sleep controller in power-down mode, standby mode, and adc noise reduction mode to avoid high power consumption if some input signals are left floating, or have an analog signal level close to v cc /2. sleep is overridden for port pins enabled as external interrupt pins. if the external interrupt request is not enabled, sleep is ac tive also for these pins. sleep is also overridden by various other alternate functions as described in ?alternate port func- tions? on page 48. if a logic high level (?one?) is present on an asynchronous external interrupt pin config- ured as ?interrupt on a rising edge, falli ng edge, or any logic change on pin? while the external interrupt is not enabled, the corresponding exte rnal interrupt flag will be set when resuming from the above mentioned sl eep modes, as the clamping in these sleep modes produces the requested logic change. assembly code example (1) ... ; define pull-ups and set outputs high ; define directions for port pins ldi r16,(1< 49 attiny26(l) 1477i?avr?10/06 table 22 summarizes the function of the overriding signals. the pin and port indexes from figure 35 are not shown in the succeed ing tables. the overriding signals are gen- erated internally in the modules having the alternate function. the following subsections shortly describes the alternate functions for each port, and relates the overriding signals to the alternate function. refer to the alternate function description for further details. table 22. generic description of overriding signals for alternate functions signal name full name description puoe pull-up override enable if this signal is set, the pull-up enable is controlled by the puov signal. if this signal is cleared, the pull-up is enabled when {ddxn, portxn, pud} = 0b010. puov pull-up override value if puoe is set, the pull-up is enabled/disabled when puov is set/cleared, regardless of the setting of the ddxn, portxn, and pud register bits. ddoe data direction override enable if this signal is set, the output driver enable is controlled by the ddov signal. if this signal is cleared, the output driver is enabled by the ddxn register bit. ddov data direction override value if ddoe is set, the output driver is enabled/disabled when ddov is set/cleared, regardless of the setting of the ddxn register bit. pvoe port value override enable if this signal is set and the output driver is enabled, the port value is controlled by the pvov signal. if pvoe is cleared, and the output driver is enabled, the port value is controlled by the portxn register bit. pvov port value override value if pvoe is set, the port value is set to pvov, regardless of the setting of the portxn register bit. dieoe digital input enable override enable if this bit is set, the digital input enable is controlled by the dieov signal. if this signal is cleared, the digital input enable is determined by mcu-state (normal mode, sleep modes). dieov digital input enable override value if dieoe is set, the digital input is enabled/disabled when dieov is set/cleared, regardless of the mcu state (normal mode, sleep modes). di digital input this is the digital input to alternate functions. in the figure, the signal is connected to the output of the schmitt trigger but before the synchronizer. unless the digital input is used as a clock source, the module with the alternate function will use its own synchronizer. aio analog input/output this is the anal og input/output to/from alternate functions. the signal is connected directly to the pad, and can be used bidirectionally. 50 attiny26(l) 1477i?avr?10/06 mcu control register ? mcucr the mcu control register contains control bits for general mcu functions. ? bit 6 ? pud: pull-up disable when this bit is set (one), the pull-ups in the i/o ports are disabled even if the ddxn and portxn registers are configured to enable the pull-ups ({ddxn, portxn} = 0b01). see ?configuring the pin? on page 44 for more details about this feature. alternate functions of port a port a has an alternate functions as analog inputs for the adc and analog comparator and pin change interrupt as shown in table 23. if some port a pins are configured as outputs, it is essential that these do not switch when a conversion is in progress. this might corrupt the result of the conversion. the adc is described in ?analog to digital converter? on page 96. analog comparator is described in ?analog comparator? on page 93. pin change interrupt triggers on pins pa7, pa6 and pa3 if interrupt is enabled and it is not masked by the alternate functions even if the pin is configured as an output. see details from ?pin change interrupt? on page 64. table 24 and table 25 relates the alternate functions of port a to the overriding signals shown in figure 35 on page 48. thera are changes on pa7, pa6, and pa3 digital inputs. pa3 output and pullup driver are also overridden. ? adc6/ain1 port ? a, bit 7 ain1: analog comparator negative input and adc6: a dc input channel 6 . configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interfering with the function of the analog comparator or analog to digital converter. pcint1: pin change interrupt 1 pin. pin chang e interrupt is enabled on pin when global interrupt is enabled, pin change interrupt is enabled and the alternate function do not mask the interrupt. the masking alternate function is the analog comparator. digital input is enabled on pin pa7 also in sleep modes, if the pin change interrupt is enabled and not masked by the alternate function. ? adc5/ain0 port ? a, bit 6 bit 76543210 $35 ($55) ?pud se sm1 sm0 ? isc01 isc00 mcucr read/write r r/w r/w r/w r/w r r/w r/w initial value00000000 table 23. port a pins alternate functions port pin alternate function pa7 adc6 (adc input channel 6) ain1 (analog comparator negative input) pcint1 (pin change interrupt 1) pa6 adc5 (adc input channel 5) ain0 (analog comparator positive input) pcint1 (pin change interrupt 1) pa5 adc4 (adc input channel 4) pa4 adc3 (adc input channel 3) pa3 aref (adc external reference) pcint1 (pin change interrupt 1) pa2 adc2 (adc input channel 2) pa1 adc1 (adc input channel 1) pa0 adc0 (adc input channel 0) 51 attiny26(l) 1477i?avr?10/06 ain0: analog comparator positive input and adc5: adc input channel 5 . configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interfering with the function of the analog comparator or analog to digital converter. pcint1: pin change interrupt 1 pin. pin chang e interrupt is enabled on pin when global interrupt is enabled, pin change interrupt is enabled and the alternate function do not mask the interrupt. the masking alternate function is the analog comparator. digital input is enabled on pin pa6 also in sleep modes, if the pin change interrupt is enabled and not masked by the alternate function. ? adc4, adc3 port ? a, bit 5, 4 adc4/adc3: adc input channel 4 and 3. configure the port pins as inputs with the internal pull-ups switched off to avoid the digital port function from interfering with the function of the analog to digital converter. ? aref/pcint1 port ? a, bit 3 aref: external reference for adc. pullup and output driver are disabled on pa3 when the pin is used as an external reference or internal voltage reference (2.56v) with external capacitor at the aref pin by setting (one) the bit refs0 in the adc multiplexer selection regist er (admux). pcint1: pin change interrupt 1 pin. pin chang e interrupt is enabled on pin when global interrupt is enabled, pin change interrupt is enabled and the alternate function do not mask the interrupt. the masking alternate function is the pin usage as an analog refer- ence for the adc. digital in put is enabled on pin pa3 al so in sleep modes, if the pin change interrupt is enabled and not masked by the alternate function. table 24. overriding signals for alternate functions in pa7..pa4 signal name pa7/adc6/ ain1/pcint1 pa6/adc5/ ain0/pcint1 pa5/adc4 pa4/adc3 puoe 0 0 0 0 puov 0 0 0 0 ddoe 0 0 0 0 ddov 0 0 0 0 pvoe 0 0 0 0 pvov 0 0 0 0 dieoe pcint1_enable (1) ? acsr[acd] pcint1_enable (1) ? acsr[acd] 00 dieov 1 1 0 0 di pcint1 pcint1 ? ? aio adc6 input, ain1 adc5 input, ain0 adc4 input adc3 input 52 attiny26(l) 1477i?avr?10/06 notes: 1. note that the pcint1 in terrupt is only enabled if bo th the global interrupt flag is enabled, the pcie1 flag in gimsk is set and the alternate function of the pin is dis- abled as described in ?pin change interrupt? on page 64 2. not operator is marked with ?~?. table 25. overriding signals for alternate functions in pa3..pa0 signal name pa3/aref/pcint1 pa2/adc2 pa1/adc1 pa0/adc0 puoe admux[refs0] 0 0 0 puov0 000 ddoe admux[refs0] 0 0 0 ddov 0 0 0 0 pvoe0 000 pvov0 000 dieoe pcint1_enable (1) ? ~ (2) admux[refs0] 000 dieov1 000 dipcint1 ??? aio analog reference input adc2 input adc1 input adc0 input 53 attiny26(l) 1477i?avr?10/06 alternate functions of port b port b has an alternate functions for the a dc, clocking, timer/counters, usi, spi pro- gramming and pin change interrupt. the adc is described in ?analog to digital converter? on page 96, clocking in ?avr cpu core? on page 8, timers in ?timer/counters? on page 66 and usi in ?universal serial interface ? usi? on page 82. pin change interrupt triggers on pins pb7 - pb0 if interrupt is enabled and it is not masked by the alternate functions even if th e pin is configured as an output. see details from ?pin change interrupt? on page 64. pin functions in programming modes are described in ?memory programming? on page 109. the alternate functions are shown in table 26. the alternate pin configuration is as follows: ? adc10/reset /pcint1 ? port b, bit 7 adc10: adc input channel 10. configure the port pins as inputs with the internal pull- ups switched off to avoid the digital port function from interfering with the function of the analog to digital converter. reset : external reset input is active low and enabled by unprogramming (?1?) the rstdisbl fuse. pullup is activated and output driver and digital input are deactivated when the pin is used as the reset pin. table 26. port b pins alternate functions port pin alternate functions pb7 adc10 (adc input channel 10) reset (external reset input) pcint1 (pin change interrupt 1) pb6 adc9 (adc input channel 9) int0 (external interrupt 0 input) t0 (timer/counter 0 external counter clock input) pcint1 (pin change interrupt 1) pb5 adc8 (adc input channel 8) xtal2 (crystal oscillator output) pcint1 (pin change interrupt 1) pb4 adc7 (adc input channel 7) xtal1 (crystal oscillator input) pcint1 (pin change interrupt 1) pb3 oc1b (timer/counter1 pwm output b, timer/counter1output compare b match output) pcint0 (pin change interrupt 0) pb2 sck (usi clock input/output) scl (usi external open-collector serial clock) oc1b (inverted timer/counter1 pwm output b) pcint0 (pin change interrupt 0) pb1 do (usi data output) oc1a (timer/counter1 pwm output a, ti mer/counter1 output compare a match output) pcint0 (pin change interrupt 0) pb0 di (usi data input) sda (usi serial data) oc1a (inverted timer/counter1 pwm output a) pcint0 (pin change interrupt 0) 54 attiny26(l) 1477i?avr?10/06 pcint1: pin change interrupt 1 pin. pin chang e interrupt is enabled on pin when global interrupt is enabled, pin change interrupt is enabled and the alternate function do not mask the interrupt. the masking alternate f unction is the pin us age as reset. digital input is enabled on pin pb7 also in sleep modes, if the pin change interrupt is enabled and not masked by the alternate function. ? adc9/int0/t0/pcint1 ? port b, bit 6 adc9: adc input channel 9. configure the port pins as inputs with the internal pull-ups switched off to avoid the digital port function from interfering with the function of the ana- log to digital converter. int0: external interrupt source 0: the pb6 pi n can serve as an external interrupt source enabled by setting (one) the bit int0 in the general input mask register (gimsk). t0: timer/counter0 external counter clock input is enabled by setting (one) the bits cs02 and cs01 in the timer/counter0 control register (tccr0). pcint1: pin change interrupt 1 pin. pin chan ge interrupt is enabled on pin when global interrupt is enabled, pin change interrupt is enabled and the alternate functions do not mask the interrupt. the masking alternate functions are the external low level interrupt source 0 (int0) and the timer/counter0 external counter clock input (t0). digital input is enabled on pin pb6 also in sleep modes, if the pin change interrupt is enabled and not masked by the alternate functions. ? adc8/xtal2/pcint1 ? port b, bit 5 adc8: adc input channel 8. configure the port pins as inputs with the internal pull-ups switched off to avoid the digital port function from interfering with the function of the ana- log to digital converter. xtal2: chip clock oscillator pin 2. used as clock pin for all chip clock sources except internal calibrateble rc oscillator, external clock and pll clock. when used as a clock pin, the pin can not be used as an i/o pin. when using internal calibratable rc oscilla- tor, external clock or pll clock as chip clock sources, pb5 serves as an ordinary i/o pin. pcint1: pin change interrupt 1 pin. pin chan ge interrupt is enabled on pin when global interrupt is enabled, pin change interrupt is enabled and the alternate functions do not mask the interrupt. the masking alternate functions are the xtal2 outputs. digital input is enabled on pin pb5 also in sleep modes, if the pin change interrupt is enabled and not masked by the alternate functions. ? adc7/xtal1/pcint1 ? port b, bit 4 adc7: adc input channel 7. configure the port pins as inputs with the internal pull-ups switched off to avoid the digital port function from interfering with the function of the ana- log to digital converter. xtal1: chip clock oscillator pin 1. used for all chip clock sources except internal cali- brateble rc oscillator and pl l clock. when used as a clock pin, the pin can not be used as an i/o pin. when using in ternal calibratable rc oscillator or pll clock as chip clock sources, pb4 serves as an ordinary i/o pin. pcint1: pin change interrupt 1 pin. pin chan ge interrupt is enabled on pin when global interrupt is enabled, pin change interrupt is enabled and the alternate functions do not mask the interrupt. the masking alternate func tions are the xtal1 inputs. digital input is enabled on pin pb4 also in sleep modes, if the pin change interrupt is enabled and not masked by the alternate functions. ? oc1b/pcint0 ? port b, bit 3 55 attiny26(l) 1477i?avr?10/06 oc1b: output compare match output: the pb3 pin can serve as an output for the timer/counter1 compare match b. the pb3 pin has to be configured as an output (ddb3 set (one)) to serve this function. the oc1b pin is also the output pin for the pwm mode. pcint0: pin change interrupt 0 pin. pin chan ge interrupt is enabled on pin when global interrupt is enabled, pin change interrupt is enabled and the alternate functions do not mask the interrupt. the masking alternate function is the output compare match output oc1b. digital input is enabled on pin pb3 al so in sleep modes, if the pin chan ge inter- rupt is enabled and not masked by the alternate functions. ? sck/scl/oc1b /pcint0 ? port b, bit 2 sck: clock input or output in usi three-wire mode. when the spi is enabled this pin is configured as an input. in the usi three-wire mode the bit ddrb2 controls the direction of the pin, output for the master mode and input for the slave mode. scl: usi external open-collector serial cl ock for usi two-wire mode. the scl pin is pulled low when portb2 is cleared (zero) or usi start condition is detected and ddrb2 is set (one). pull-up is disabled in usi two-wire mode. oc1b : inverted timer/counter1 pwm output b: the pb2 pin can serve as an inverted output for the timer/counter1 pwm mode if usi is not enabled. the pb2 pin has to be configured as an output (ddb2 set (one)) to serve this function. pcint1: pin change interrupt 0 pin. pin chan ge interrupt is enabled on pin when global interrupt is enabled, pin change interrupt is enabled and the alternate functions do not mask the interrupt. the masking alternate function are the inverted output compare match output oc1b and usi clocks sck/scl. digi tal input is enabled on pin pb2 also in sleep modes, if the pin change interrupt is enabled and not masked by the alternate functions. ? do/oc1a/pcint0 ? port b, bit 1 do: data output in usi three-wire mode. data output (do) overrides portb1 value and it is driven to the port when the data di rection bit ddb1 is set (one). however the portb1 bit still controls the pullup, enabli ng pullup if direction is input and portb1 is set(one). oc1a: output compare match output: the pb1 pin can serve as an output for the timer/counter1 compare match a. the pb1 pin has to be configured as an output (ddb1 set (one)) to serve this function. the oc1b pin is also the output pin for the pwm mode timer function if not used in programming or usi. pcint0: pin change interrupt 0 pin. pin chan ge interrupt is enabled on pin when global interrupt is enabled, pin change interrupt is enabled and the alternate functions do not mask the interrupt. the masking alternate functions are the output compare match out- put oc1a and data output (do) in usi thre e-wire mode. digital inpu t is enabled on pin pb1 also in sleep modes, if the pin change interrupt is enabled and not masked by the alternate functions. 56 attiny26(l) 1477i?avr?10/06 ? di/sda/oc1a/ pcint0 ? port b, bit 0 di: data input in usi three-wire mode. usi three-wire mode does not override normal port functions., so pin must be configure as an input. sda: serial data in usi two-wire mode. seri al data pin is bi-directional and uses open- collector output. the sda pin is enabled by setting the pin as an output. the pin is pulled low when the portb0 or usi shiftregis ter is zero when ddb0 is set (one). pull- up is disabled in usi two-wire mode. oc1a : inverted timer/counter1 pwm output a: the pb0 pin can serve as an inverted output for the pwm mode if not used in programming or usi. the pb0 pin has to be configured as an output (ddb0 set (one)) to serve this function. pcint0: pin change interrupt 0 pin. pin chan ge interrupt is enabled on pin when global interrupt is enabled, pin change interrupt is enabled and the alternate functions do not mask the interrupt. the masking alternate functions are the inverted output compare match output oc1a and usi data di or sda. digital input is enabled on pin pb0 also in sleep modes, if the pin change interrupt is enabled and not masked by the alternate functions. table 27 and table 28 relate the al ternate functions of port b to the overriding signals shown in ?alternate port functions? on page 48. notes: 1. rstdisbl fuse (active low) is described in section ?system control and reset? on page 33. 2. note that the pcint1 interrupt is only enabled if both the gl obal interrupt flag is enabled, the pcie1 flag in gimsk is set and the alternate function of the pin is disabled as described in ?pin change interrupt? on page 64. 3. pb5ioenable and pb4ioenable are given by the pllck and cksel fuses as described in ?clock sources? on page 26. 4. external low level interrupt is enabled if both the global in terrupt flag is enabled and the int0 flag in gimsk is set as described in ?external interrupt? on page 64. 5. not operator is marked with ?~?. 6. the operation of the timer/counter0 with external clock di sabled is described in ?8-bit timer/counter0? on page 67. 7. external clock is selected by the pllck and cksel fuses as described in ?clock sources? on page 26. table 27. overriding signals for alternate functions in pb7..pb4 signal name pb7/adc10/reset/ pcint1 pb6/adc9/int0/to/ pcint1 pb5/adc8/xtal2/ pcint1 pb4/adc7/xtal1 puoe rstdsbl (1) 0~ (5) pb5ioenable (3) ~pb4ioenable (3) puov 1 0 0 0 ddoe rstdsbl (1) 0 ~pb5ioenable (3) ~pb4ioenable (3) ddov 0 0 0 0 pvoe 0 0 0 0 pvov 0 0 0 0 dieoe pcint1_enable (2) | rstdsbl (1) ~t0_ext_clock (6) ? pcint1_enable (2) | int0_enable (4) pcint1_enable (2) | ~pb5ioenable (3) pcint_ enable (2) | ~pb4ioenable (3) | ext_clock_enable (7) dieov pcint1_enable (2) ? ~ (5) rstdsbl (1) 1 pcint1_enable (2) ? pb5ioenable (3) pcint1_enable (2) ? pb4ioenable (3) | ext_clock_enable di pcint1 int0, t0, pcint1 pcint1 external clock, pcint1 aio adc10, reset input adc9 adc8, xtal2 xtal1 57 attiny26(l) 1477i?avr?10/06 notes: 1. enabling of the timer/counter1 compare match ou tputs and timer/counter1 pwm outputs oc1a/oc1b and oc1a /oc1b are described in the section ?8-bit timer/counter1? on page 69. 2. note that the pcint0 interrupt is only enabled if both the gl obal interrupt flag is enabled, the pcie0 flag in gimsk is set and the alternate function of the pin is disabled as described in ?pin change interrupt? on page 64. 3. the two-wire and three-wire usi-modes are described in ?universal serial interface ? usi? on page 82. 4. shift clock (scl) hold for usi is in described ?universal serial interface ? usi? on page 82. 5. usi start up interrupt is enabled if both t he global interrupt flag is enabled and the usisie flag in the usicr register is s et as described in ?universal serial interface ? usi? on page 82. 6. data output (do) is valid in usi three-wire mode and the oper ation is described in ?universal serial interface ? usi? on page 82. 7. operation of the data pin sda in usi two- wire mode and di in usi three-wire mode in ?universal serial interface ? usi? on page 82. 8. not operator is marked with ?~?. table 28. overriding signals for alternate functions in pb3..pb0 signal name pb3/oc1b/pcint0 pb2/sck/scl/oc1b /pci nt0 pb1/do/oc1a/pcint0 pb0/di/sda/oc1a puoe 0 usi_two-wire (3) 0 usi_two-wire (3) puov0000 ddoe 0 usi_two-wire (3) 0usi_two-wire (3) ddov 0 (usi_scl_hold (4) | ~ (8) portb2) ? ddb2 0 (~sda | ~portb0) ? ddb0 pvoe oc1b_enable (1) usi_two-wire (3) ? ddb2 | oc1b_enable (1) usi_three-wire (3) | oc1a_enable (1) usi_two-wire (3) ? ddb0 | oc1a _enable (1) pvov oc1b ~(usi_two-wire ? ddb2) ? oc1b usi_three-wire (3) ? do (6) | ~usi_three- wire ? oc1a_enable (1) ? oc1a ~(usi_two-wire? ddb0) ? oc1a _enable (1) ? oc1a dieoe pcint0_enable (2) ? ~oc1b_enable (1) ~(usi_two-wire | usi_three-wire | oc1b _enable) ? pcint0_enable (2) | usi_start_i.enable (5) ~(usi_three-wire | oc1a_enable) ? pcint0_enable (2) ~(usi_two-wire (3) | usi_three-wire (3) | oc1a _enable (1) ) ? pcint0_enable (2) | usi_start_i.enable (5) dieov1111 di pcint0 pcint0, scl, sck pcint0 pcint0, sda aio???? 58 attiny26(l) 1477i?avr?10/06 register description for i/o ports port a data register ? porta port a data direction register ? ddra port a input pins address ? pina port b data register ? portb port b data direction register ? ddrb port b input pins address ? pinb bit 76543210 $1b ($3b) porta7 porta6 porta5 porta4 porta3 porta2 porta1 porta0 porta read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 $1a ($3a) dda7 dda6 dda5 dda4 dda3 dda2 dda1 dda0 ddra read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 $19 ($39) pina7 pina6 pina5 pina4 pi na3 pina2 pina1 pina0 pina read/writerrrrrrrr initial value n/a n/a n/a n/a n/a n/a n/a n/a bit 76543210 $18 ($38) portb7 portb6 portb5 portb4 portb3 portb2 portb1 portb0 portb read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 $17 ($37) ddb7 ddb6 ddb5 ddb4 ddb3 ddb2 ddb1 ddb0 ddrb read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 $16 ($36) pinb7 pinb6 pinb5 pinb4 pi nb3 pinb2 pinb1 pinb0 pinb read/writerrrrrrrr initial value n/a n/a n/a n/a n/a n/a n/a n/a 59 attiny26(l) 1477i?avr?10/06 interrupts interrupt vectors the attiny26(l) provides eleven interrupt sources. these interrupts and the separate reset vector, each have a separate program vector in the program memory space. all the interrupts are assigned individual enable bi ts which must be set (one) together with the i-bit in the status register in order to enable the interrupt. the lowest addresses in the program memory space are automatically defined as the reset and interrupt vectors. the complete list of vectors is shown in table 29. the list also determines the priority levels of the different interrupts. the lower the address the higher is the priority level. reset has the highest priority, and nex t is int0 ? the exter- nal interrupt request 0 etc. the most typical and general program setup for the reset and interrupt vector addresses are: address labels code comments $000 rjmp reset ; reset handler $001 rjmp ext_int0 ; irq0 handler $002 rjmp pin_change ; pin change handler $003 rjmp tim1_cmp1a ; timer1 compare match 1a $004 rjmp tim1_cmp1b ; timer1 compare match 1b $005 rjmp tim1_ovf ; timer1 overflow handler $006 rjmp tim0_ovf ; timer0 overflow handler $007 rjmp usi_strt ; usi start handler $008 rjmp usi_ovf ; usi overflow handler $009 rjmp ee_rdy ; eeprom ready handler $00a rjmp ana_comp ; analog comparator handler $00b rjmp adc ; adc conversion handler ; $009 reset: ldi r16, ramend ; main program start $00a out sp, r16 table 29. reset and interrupt vectors vector no program address source interrupt definition 1 $000 reset hardware pin and watchdog reset 2 $001 int0 external interrupt request 0 3 $002 i/o pins pin change interrupt 4 $003 timer1, cmpa timer/counter1 compare match 1a 5 $004 timer1, cmpb timer/counter1 compare match 1b 6 $005 timer1, ovf1 timer/counter1 overflow 7 $006 timer0, ovf0 timer/counter0 overflow 8 $007 usi_strt usi start 9 $008 usi_ovf usi overflow a $009 ee_rdy eeprom ready b $00a ana_comp analog comparator c $00b adc adc conversion complete 60 attiny26(l) 1477i?avr?10/06 $00b sei ? ? ? ? interrupt handling the attiny26(l) has two 8-bit interrupt mask control registers; gimsk ? general inter- rupt mask register and timsk ? timer/counter interrupt mask register. when an interrupt occurs, the global interrupt enable i-bit is cleared (zero) and all inter- rupts are disabled. the user software can set (one) the i-bit to enable nested interrupts. the i-bit is set (one) when a return from interrupt instruction ? reti ? is executed. when the program counter is vectored to the actual interrupt vector in order to execute the interrupt handling routine, hardware clears the corresponding flag that generated the interrupt. some of the interrupt flags can also be cleared by writing a logic one to the flag bit position(s) to be cleared. if an interrupt condition occurs when the corresponding interrupt enable bit is cleared (zero), the interrupt flag will be set and remembered until the in terrupt is enab led, or the flag is cleared by software. if one or more interrupt conditions occur w hen the global interrupt enable bit is cleared (zero), the corresponding interrupt flag(s) will be set and remembered until the global interrupt enable bit is set (one), and will be executed by order of priority. note that external level in terrupt does not hav e a flag, and will only be remembered for as long as the interrup t condition is active. note that the status register is not automatically stored when entering an interrupt rou- tine and restored when returning from an interrupt routine. this must be handled by software. interrupt response time the interrupt execution response for all the enabled avr interrupts is four clock cycles minimum. after the four clock cycles the program vector address for the actual interrupt handling routine is executed. during this four clock cycle period, the program counter (10 bits) is pushed onto the stack. the vector is a relative jump to the interrupt routine, and this jump takes two clock cycles. if an in terrupt occurs during execution of a multi- cycle instruction, this instruction is co mpleted before the interrupt is served. a return from an interrupt handling routine ta kes four clock cycles. during these four clock cycles, the program counter (10 bits) is popped back from the stack. when avr exits from an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served. note that the status register ? sreg ? is not handled by the avr hardware, neither for interrupts nor for subroutines. for the routines requiring a storage of the sreg, this must be performed by user software. general interrupt mask register ? gimsk ? bit 7 ? res: reserved bit this bit is a reserved bit in the attiny26(l) and always reads as zero. ? bit 6 ? int0: external interrupt request 0 enable when the int0 bit is set (one) and the i-bit in the status register (sreg) is set (one), the external pin interrupt is enabled. the interrupt sense control0 bits 1/0 (isc01 and isc00) in the mcu general control regist er (mcucr) define whether the external bit 76543210 $3b ($5b) ? int0 pcie1 pcie0 ? ? ? ? gimsk read/write r r/w r/w r/w r r r r initial value00000000 61 attiny26(l) 1477i?avr?10/06 interrupt is activated on rising or falling edge, on pi n change, or low level of the int0 pin. activity on the pin will cause an interrupt request even if int0 is configured as an output. the corresponding interrupt of external interrupt request 0 is executed from program memory address $001. see also ?external interrupt? on page 64. ? bit 5 ? pcie1: pin change interrupt enable1 when the pcie1 bit is set (one) and the i-bit in the status register (sreg) is set (one), the interrupt pin change is enabled on analog pins pb[7:4], pa[7:6] and pa[3]. unless the alternate function masks out the interr upt, any change on the pin mentioned before will cause an interrupt. the corresponding interrupt of pin change interrupt request is executed from program memory address $002. see also ?pin change interrupt? on page 64. ? bit 4? pcie0: pin change interrupt enable0 when the pcie0 bit is set (one) and the i-bit in the status register (sreg) is set (one), the interrupt pin change is enabled on digital pins pb[3:0]. unless the alternate function masks out the inte rrupt, any change on the pin mentioned before will cause an interrupt. the corresponding interrupt of pin change interrupt request is executed from program memory address $002. see also ?pin change interrupt? on page 64. ? bits 3..0 ? res: reserved bits these bits are reserved bits in the attiny26(l) and always read as zero. general interrupt flag register ? gifr ? bit 7 ? res: reserved bit this bit is a reserved bit in the attiny26(l) and always reads as zero. ? bit 6 ? intf0: external interrupt flag0 when an event on the int0 pin triggers an interrupt request, intf0 becomes set (one). if the i-bit in sreg and the int0 bit in gimsk are set (one), the mcu will jump to the interrupt vector at address $001. the flag is cleared when the interrupt routine is exe- cuted. alternatively, the flag can be cleared by writing a logical one to it. the flag is always cleared when int0 is co nfigured as le vel interrupt. ? bit 5 ? pcif: pin change interrupt flag when an event on pins pb[7:0], pa[7:6], or pa[3] triggers an interrupt request, pcif becomes set (one). pcie1 enables interrupt from analog pins pb[7:4], pa[7:6], and pa[3]. pcie0 enables interrupt on digital pi ns pb[3:0]. note that pin change interrupt enable bits pcie1 and pcie0 also mask the fl ag if they are not set. for example, if pcie0 is cleared, a pin change on pb[3:0] doe s not set pcif. if an alternate function is enabled on a pin, pcif is masked from that individual pin. if the i-bit in sreg and the pcie bit in gimsk are set (one), the mcu will jump to the interrupt vector at address $002. the flag is cleared when the interrupt r outine is executed. alternatively, the flag can be cleared by writing a logical one to it. see also ?pin change interrupt? on page 64. ? bits 4..0 ? res: reserved bits these bits are reserved bits in the attiny26(l) and always read as zero. timer/counter interrupt mask register ? timsk bit 76543210 $3a ($5a) ? intf0 pcif ? ? ? ? ? gifr read/write r r/w r/w r r r r r initial value00000000 bit 7 6 5 4 3 2 1 0 $39 ($59) ? ocie1a ocie1b ? ? toie1 toie0 ? timsk 62 attiny26(l) 1477i?avr?10/06 ? bit 7 ? res: reserved bit this bit is a reserved bit in the attiny26(l) and always reads as zero. ? bit 6 ? ocie1a: timer/counter1 output compare interrupt enable when the ocie1a bit is set (one) and the i-bit in the status register is set (one), the timer/counter1 compare match a, interrupt is enabled. the corresponding interrupt at vector $003 is executed if a compare match a occurs. the compare flag in timer/counter1 is set (one) in the timer/counter interrupt flag register. ? bit 5 ? ocie1b: timer/counter1 output compare interrupt enable when the ocie1b bit is set (one) and the i-bit in the status register is set (one), the timer/counter1 compare match b, interrupt is enabled. the corresponding interrupt at vector $004 is executed if a compare match b occurs. the compare flag in timer/counter1 is set (one) in the timer/counter interrupt flag register. ? bit 4..3 ? res: reserved bits these bits are reserved bits in the attiny26(l) and always read as zero. ? bit 2 ? toie1: timer/counter1 overflow interrupt enable when the toie1 bit is set (one) and the i-bit in the status register is set (one), the timer/counter1 overflow interrupt is enabled. the corresponding interrupt (at vector $005) is executed if an overflow in timer/ counter1 occurs. the overflow flag (timer1) is set (one) in the timer/counter interrupt flag register ? tifr. ? bit 1 ? toie0: timer/counter0 overflow interrupt enable when the toie0 bit is set (one) and the i-bit in the status register is set (one), the timer/counter0 overflow interrupt is enabled. the corresponding interrupt (at vector $006) is executed if an overflow in timer/ counter0 occurs. the overflow flag (timer0) is set (one) in the timer/counter interrupt flag register ? tifr. ? bit 0 ? res: reserved bit this bit is a reserved bit in the attiny26(l) and always reads as zero. timer/counter interrupt flag register ? tifr ? bit 7 ? res: reserved bit this bit is a reserved bit in the attiny26(l) and always reads as zero. ? bit 6 ? ocf1a: output compare flag 1a the ocf1a bit is set (one) when compare match occurs between timer/counter1 and the data value in ocr1a ? output compare register 1a. ocf1a is cleared by hard- ware when executing the corresponding interrupt handling vector. alternatively, ocf1a is cleared, after synchronization clock cycle, by writing a logic one to the flag. when the i-bit in sreg, ocie1a, and ocf1a are set (one), the timer/counter1 a compare match interrupt is executed. ? bit 5 ? ocf1b: output compare flag 1b the ocf1b bit is set (one) when compare match occurs between timer/counter1 and the data value in ocr1b ? output compare register 1a. ocf1b is cleared by hard- read/write r r/w r/w r r r/w r/w r initial value 0 0 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 $38 ($58) ? ocf1a ocf1b ? ? tov1 tov0 ? tifr read/write r r/w r/w r r r/w r/w r initial value 0 0 0 0 0 0 0 0 63 attiny26(l) 1477i?avr?10/06 ware when executing the corresponding interrupt handling vector. alternatively, ocf1b is cleared, after synchronization clock cycle, by writing a logic one to the flag. when the i-bit in sreg, ocie1b, and ocf1b are set (one), the timer/counter1 b compare match interrupt is executed. ? bits 4..3 ? res: reserved bits these bits are reserved bits in the attiny26(l) and always read as zero. ? bit 2 ? tov1: timer/counter1 overflow flag the bit tov1 is set (one) when an overflow occurs in timer/counter1. tov1 is cleared by hardware when executing the corresponding interrupt handling vector. alternatively, tov1 is cleared, after synchronization clock cy cle, by writing a logical one to the flag. when the sreg i-bit, and toie1 (timer /counter1 overflow interrupt enable), and tov1 are set (one), the timer/counter1 overflow interrupt is executed. ? bit 1 ? tov0: timer/counter0 overflow flag the bit tov0 is set (one) when an overflow occurs in timer/counter0. tov0 is cleared by hardware when executing the corresponding interrupt handling vector. alternatively, tov0 is cleared by writing a logical one to the flag. when the sreg i-bit, and toie0 (timer/counter0 overflow interrupt enable), and tov0 are set (one), the timer/counter0 overflow interrupt is executed. ? bit 0 ? res: reserved bit this bit is a reserved bit in the attiny26(l) and always reads as zero. 64 attiny26(l) 1477i?avr?10/06 external interrupt the external interrupt is triggered by the int0 pin. observe that, if enabled, the interrupt will trigger even if the in t0 pin is configured as an output. this f eature provides a way of generating a software interrupt. the external interrupt can be triggered by a falling or rising edge, a pin change, or a low level. this is set up as indicated in the specification for the mcu control register ? mcucr. when the external interrupt is enabled and is configured as level triggered, the interrupt will trigger as long as the pin is held low. the changed level is sampled twice by the wa tchdog oscillator clock, and if both these samples have the required level, the mcu will wake up. the period of the watchdog oscillator is 1.0 s (nominal) at 3.0v and 25c. the fr equency of the watchdog oscilla- tor is voltage dependent as shown in ?electrical characteristics? on page 128. pin change interrupt the pin change interrupt is triggered by any change on any i/o pin of port b and pins pa3, pa6, and pa7, if the interrupt is enabled and alternate function of the pin does not mask out the interrupt. the bit pcie1 in gimsk enables interrupt from pins pb[7:4], pa[7:6], and pa[3]. pcie0 enables interrupt on digital pins pb[3:0]. the pin change interrupt is different from other interrupts in two ways. first, pin change interrupt enable bits pcie1 and pcie0 also mask the flag if they are not set. the normal operation on most interrupts is that the flag is always active and only the execution of the interrupt is masked by the interrupt enable. secondly, please note that pin change interrup t is disabled for any pin that is configured as an alternate function. for example, no pin change interrupt is generated from pins that are configured as aref, ain0 or ain1, oc1a, oc1a , oc1b, oc1b , xtal1, or xtal2 in a fuse selected clock opt ion, timer0 clocking, or reset function. see table 30 for alternate functions which mask the pin change interrupt and how the function is enabled. for example pin change interrupt on the pb0 is disabled when usi two-wire mode or usi three-wire mode or timer/counter1 inverted output compare is enabled. if the interrupt is enabled, th e interrupt will trigger even if the changing pin is configured as an output. this feature provides a way of generating a software interrupt. also observe that the pin change interrupt will trigger even if the pin activity triggers another interrupt, for example the external interrupt. this implies that one external event might cause several interrupts. the value of the programmed fuse is ?0? and unprogrammed is ?1?. each of the lines enables the alternate function so ?or? function of the lines enables the function. 65 attiny26(l) 1477i?avr?10/06 notes: 1. each line represents a bit or fuse combination which enables the function. a fuse value of ?0? is programmed, ?1? is unprogrammed. table 30. alternative functions pin alternate function control register[bit name] which set the alternate function (1) bit or fuse value () pa3 aref admux[refs0] 1 pa6 analog comparator acsr[acd] 0 pa7 analog comparator acsr[acd] 0 pb0 usi two-wire mode usi three-wire mode tc1 compare/pwm usicr[usiwm1] usicr[usiwm1,usiwm0] tccr1a[com1a1,com1a0,pwm1a] 1 01 011 pb1 usi three-wire mode tc1 compare/pwm usicr[usiwm1,usiwm0] tccr1a[com1a1] tccr1a[com1a0] 01 1 1 pb2 usi two-wire mode usi three-wire mode tc1 compare/pwm usicr[usiwm1] usicr[usiwm1,usiwm0] tccr1a[com1b1,com1b0,pwm1b] 1 01 011 pb3 tc1 compare/pwm tccr1a[com1b1] tccr1a[com1b0] 1 1 pb4 xtal1, clock source fuse[pllck,cksel] fuse[pllck,cksel] 10000 10101-11111 pb5 xtal2, clock source fuse[pllck,cksel] 11001-11111 pb6 external interrupt tc0 clock gimsk[int0],mcucr[isc01,isc01] tccr0[cs02,cs01] 100 11 pb7 reset rstdisbl fuse 1 66 attiny26(l) 1477i?avr?10/06 timer/counters the attiny26(l) provides two general purpose 8-bit timer/counters. the timer/counters have separate prescaling selection from the separate prescaler. the timer/counter0 clock (ck) as the clock ti mebase. the timer/counter1 has two clocking modes, a synchronous mode and an asynchronous mode. the synchronous mode uses the system clock (ck) as the clock timebase and asynchronous mode uses the fast peripheral clock (pck) as the clock time base. timer/counter0 prescaler figure 36 below shows the timer/counter prescaler. figure 36. timer/counter0 prescaler the four prescaled selections are: ck/8, ck/64, ck/256, and ck/1024 where ck is the oscillator clock. ck, external source, and st op, can also be selected as clock sources. 10-bit t/c prescaler 0 timer/counter0 clock source ck t0(pb6) psr0 clear cs00 cs01 cs02 ck/8 ck/256 ck/1024 ck/64 67 attiny26(l) 1477i?avr?10/06 timer/counter1 prescaler figure 37 shows the timer/counter1 prescaler. for timer/counter1 the clock selections are between pck to pck/16384 and stop in asynchronous mode and ck to ck/16384 and stop in synchronous. the clock options are described in table 34 on page 74 and the timer/counter1 control register, tccr1 b. setting the psr1 bit in tccr1b regis- ter resets the prescaler. the pcke bi t in the pllcsr register enables the asynchronous mode. figure 37. timer/counter1 prescaler 8-bit timer/counter0 figure 38 shows the block diagram for timer/counter0. the 8-bit timer/counter0 can select clock source from ck, prescaled ck, or an external pin. in addition, it can be stopped as de scribed in the specification for the timer/counter0 control register ? tccr0. th e overflow status flag is found in the timer/counter interrupt flag register ? tifr. control signals are found in the timer/counter0 control register ? tccr0. the interrupt enable/disable settings for timer/counter0 are found in the timer/counter interrupt mask register ? timsk. when timer/counter0 is externally clocked, the external signal is synchronized with the oscillator frequency of the cpu. to ensure proper samp ling of the external clock, the minimum time between two external clock transitions must be at least one internal cpu clock period. the external clock signal is sampled on the rising edge of the internal cpu clock. the 8-bit timer/counter0 features both a high resolution and a high accuracy usage with the lower prescaling opportunities. similarly, the high prescaling opportunities make the timer/counter0 useful for lower speed functions or exact timing functions with infre- quent actions. timer/counter1 count enable psr1 cs10 cs11 cs12 pck (64 mhz) 0 cs13 14-bit t/c prescaler t1ck/2 t1ck t1ck/4 t1ck/8 t1ck/16 t1ck/32 t1ck/64 t1ck/128 t1ck/256 t1ck/512 t1ck/1024 t1ck/2048 t1ck/4096 t1ck/8192 t1ck/16384 s a ck pcke t1ck 68 attiny26(l) 1477i?avr?10/06 figure 38. timer/counter0 block diagram timer/counter0 control register ? tccr0 ? bits 7..4 ? res: reserved bits these bits are reserved bits in the attiny26(l) and always read as zero. ? bit 3 ? psr0: prescaler reset timer/counter0 when this bit is set (one), the prescaler of the timer/counter0 will be reset. the bit will be cleared by hardware after the operation is performed. writing a zero to this bit will have no effect. this bit will always be read as zero. ? bits 2, 1, 0 ? cs02, cs01, cs00: clock select0, bit 2, 1, and 0 the clock select0 bits 2, 1, and 0 define the prescaling source of timer0. bit 7 6 5 4 3 210 $33 ($53) ? ? ? ? psr0 cs02 cs01 cs00 tccr0 read/write r r r r r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 table 31. clock 0 prescale select cs02 cs01 cs00 description 0 0 0 stop, the timer/counter0 is stopped 001ck 010ck/8 011ck/64 100ck/256 101ck/1024 1 1 0 external pin t0, falling edge 1 1 1 external pin t0, rising edge 69 attiny26(l) 1477i?avr?10/06 the stop condition provides a timer en able/disable function. the ck down divided modes are scaled directly from the ck oscillator clock. if the external pin modes are used, the corresponding setup must be performed in the actual data direction control register (cleared to zero gives an input pin). timer/counter0 ? tcnt0 the timer/counter0 is implemented as an up-counter with read and write access. if the timer/counter0 is written and a clock source is present, the timer/counter0 continues counting in the timer clock cycle following the write operation. 8-bit timer/counter1 the timer/counter1 has two clocking modes: a synchronous mode and an asynchro- nous mode. the synchronous mode uses the sy stem clock (ck) as the clock timebase and asynchronous mode uses the fast peripheral clock (pck) as the clock time base. the pcke bit from the pllcsr register enables the asynchronous mode when it is set (?1?). the timer/counter1 general operation is described in the asynchronous mode and the operation in the synchronous mode is mentioned only if there is differences between these two modes. figure 39 shows timer/counter1 synchronization register block dia- gram and synchronization delays in between registers. note that all clock gating details are not shown in the figure. the timer/counter1 register values go through the internal synchronization registers, which cause the input synchronization delay, before affecting the counter operation. the registers tccr1a, tccr1b, ocr1a, ocr1b, and ocr1c can be read back right after writing the register. the read back values are delayed for the timer/counter1 (tcnt1) register and flags (ocf1a, ocf1b, and tov1), because of the input and output synchronization. this module features a high resolution and a high accuracy usage with the lower pres- caling opportunities. timer/counter1 can also support two accurate, high speed, 8-bit pulse width modulators using clock speeds up to 64 mhz. in this mode, timer/counter1 and the output compare registers serve as dual stand-alone pwms with non-overlap- ping non-inverted and inverted outputs. refer to page 76 for a detailed description on this function. similarly, the high prescaling oppor tunities make this unit useful for lower speed functions or exact timing functions with infrequent actions. bit 76543210 $32 ($52) msb lsb tcnt0 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 70 attiny26(l) 1477i?avr?10/06 figure 39. timer/counter1 synchronization register block diagram timer/counter1 and the prescaler allow running the cpu from any clock source while the prescaler is operating on the fast 64 mhz pck clock in the asynchronous mode. note that the system clock frequency must be lower than one half of the pck frequency. only when the system clock is generated from pck dividing that by two, the ratio of the pck/system clock can be exactly two. the sy nchronization mechanism of the asynchro- nous timer/counter1 needs at least two edges of the pck when the system clock is high. if the frequency of the system clock is too high, it is a risk that data or control val- ues are lost. the following figure 40 shows the block diagram for timer/counter1. ocr1a 8-bit databus sync mode 1ck delay tcnt1 ck ocf1a ocf1b tcnt1 tov1 ocr1b ocr1c tccr1a tccr1b ocr1a_si ocr1b_si ocr1c_si tccr1a_si tccr1b_si tcnt1 ocf1a ocf1b tov1 tcnt1_si ocf1a_si ocf1b_si tov1_si tcnt_so ocf1a_so ocf1b_so tov1_so s a async mode 1pck delay 1/2pck -1ck delay 1/2pck -1ck delay pck pcke s a s a s a s a s a no delay no delay io-registers input syncronization registers timer/counter1 output multiplexers output syncronization registers 71 attiny26(l) 1477i?avr?10/06 figure 40. timer/counter1 block diagram three status flags (overflow and compare matches) are found in the timer/counter interrupt flag register ? tifr. control sign als are found in the timer/counter control registers tccr1a and tccr1b. the interrupt enable/disable setting s are found in the timer/counter interrupt mask register ? timsk. the timer/counter1 contains three output compare registers, ocr1a, ocr1b, and ocr1c, as the data source to be compared with the timer/counter1 contents. in nor- mal mode the output compare functions are operational with all three output compare registers. ocr1a determine s action on the oc1a pin (pb1), and it can generate timer1 oc1a interrupt in normal mode and in pwm mode. likewise, ocr1b deter- mines action on the oc1b pin (pb3) and it can generate timer1 oc1b interrupt in normal mode and in pwm mode. ocr1c holds the timer/counter maximum value, i.e., the clear on compare match value. an overflow interrupt (tov1) is generated when timer/counter1 counts from $ff to $00 or from ocr1c to $00. this function is the same for both normal and pwm mode. the inverted pwm outputs oc1a and oc1b are not connected in normal mode. in pwm mode, ocr1a and ocr1b provide the data values against which the timer/counter value is compared. upon compare match the pwm outputs (oc1a, oc1a , oc1b, oc1b ) are generated. in pwm mode, the timer/counter counts up to the value specified in the output compare register ocr1c and starts again from $00. this feature allows limiting the counter ?full? value to a specified value, lower than $ff. together with the many prescaler options, flexible pwm frequency selection is provided. table 37 lists clock selection and ocr1c values to obtain pwm frequencies from 20 khz to 250 khz in 10 khz steps and from 25 0 khz to 500 khz in 50 khz steps. higher pwm frequencies can be obtained at the expense of resolution. 8-bit data bus timer int. flag register (tifr) timer/counter1 8-bit comparator t/c1 output compare register timer int. mask register (timsk) timer/counter1 (tcnt1) t/c clear t/c1 control logic tov1 ocf1b ocf1b tov1 toie0 toie1 ocie1b ocie1a ocf1a ocf1a ck pck t/c1 over- flow irq t/c1 compare match b irq oc1a (pb1) t/c1 compare match a irq t/c control register 1 (tccr1a) com1b1 pwm1a pwm1b com1b0 foc1a foc1b (ocr1a) (ocr1b) (ocr1c) 8-bit comparator t/c1 output compare register tov0 com1a1 com1a0 t/c control register 1 (tccr1a) oc1a (pb0) oc1b (pb3) oc1b (pb2) 8-bit comparator t/c1 output compare register t/c control register 1 (tccr1b) cs12 psr1 cs11 cs10 cs13 ctc1 72 attiny26(l) 1477i?avr?10/06 timer/counter1 control register a ? tccr1a ? bits 7, 6 ? com1a1, com1a0: comparator a output mode, bits 1 and 0 the com1a1 and com1a0 control bits determine any output pin action following a compare match with compare register a in timer/counter1. output pin actions affect pin pb1 (oc1a). since this is an alternativ e function to an i/o port, the corresponding direction control bit must be set (one) in order to control an output pin. note that oc1a is not connected in normal mode. in pwm mode, these bits have different functions. refer to table 35 on page 77 for a detailed description. ? bits 5, 4 ? com1b1, com1b0: comparator b output mode, bits 1 and 0 the com1b1 and com1b0 control bits determine any output pin action following a compare match with compare register b in timer/counter1. output pin actions affect pin pb3 (oc1b). since this is an alternativ e function to an i/o port, the corresponding direction control bit must be set (one) in order to control an output pin. note that oc1b is not connected in normal mode. in pwm mode, these bits have different functions. refer to table 35 on page 77 for a detailed description. ? bit 3 ? foc1a: force output compare match 1a writing a logical one to this bit forces a change in the compare match output pin pb1 (oc1a) according to the values already set in com1a1 and com1a0. if com1a1 and com1a0 written in the same cycle as fo c1a, the new settings will be used. the force output compare bit can be used to change the output pin value regardless of the timer value. the automatic action programmed in com1a1 and com1a0 takes place as if a compare match had occurred, but no interrupt is generated. the foc1a bit always reads as zero. foc1a is not in use if pwm1a bit is set. ? bit 2 ? foc1b: force output compare match 1b bit 7 6 5 4 3 2 1 0 $30 ($50) com1a1 com1a0 com1b1 com1b0 foc1a foc1b pwm1a pwm1b tccr1a read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 table 32. comparator a mode select com1a1 com1a0 description 0 0 timer/counter comparator a disco nnected from output pin oc1a. 0 1 toggle the oc1a output line. 1 0 clear the oc1a output line. 1 1 set the oc1a output line. table 33. comparator b mode select com1b1 com1b0 description 0 0 timer/counter comparator b disco nnected from output pin oc1b. 0 1 toggle the oc1b output line. 1 0 clear the oc1b output line. 1 1 set the oc1b output line. 73 attiny26(l) 1477i?avr?10/06 writing a logical one to this bit forces a change in the compare match output pin pb3 (oc1b) according to the values already set in com1b1 and com1b0. if com1b1 and com1b0 written in the same cycle as fo c1b, the new settings will be used. the force output compare bit can be used to change the output pin value regardless of the timer value. the automatic action programmed in com1b1 and com1b0 takes place as if a compare match had occurred, but no interrupt is generated. the foc1b bit always reads as zero. foc1b is not in use if pwm1b bit is set. ? bit 1 ? pwm1a: pulse width modulator a enable when set (one) this bit enables pwm mode based on comparator ocr1a in timer/counter1 and the counter value is reset to $00 in the cpu clock cycle after a compare match with ocr1c register value. ? bit 0 ? pwm1b: pulse width modulator b enable when set (one) this bit enables pwm mode based on comparator ocr1b in timer/counter1 and the counter value is reset to $00 in the cpu clock cycle after a compare match with ocr1c register value. timer/counter1 control register b ? tccr1b ? bit 7 ? ctc1: clear timer/counter on compare match when the ctc1 control bit is set (one), time r/counter1 is reset to $00 in the cpu clock cycle after a compare match with ocr1c register value. if the control bit is cleared, timer/counter1 continues counting and is unaffected by a compare match. ? bit 6 ? psr1: prescaler reset timer/counter1 when this bit is set (one), the timer/counter prescaler will be reset. the bit will be cleared by hardware after the operation is pe rformed. writing a zero to this bit will have no effect. this bit will always read as zero. ? bit 5..4 ? res: reserved bits these bits are reserved bits in the attiny26(l) and always read as zero. bit 7 6 5 4 3 2 1 0 $2f ($4f) ctc1 psr1 ? ? cs13 cs12 cs11 cs10 tccr1b read/write r/w r/w r r r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 74 attiny26(l) 1477i?avr?10/06 ? bits 3..0 ? cs13, cs12, cs11, cs10: clock select bits 3, 2, 1, and 0 the clock select bits 3, 2, 1, and 0 define the prescaling source of timer/counter1. the stop condition provides a timer enable/disable function. timer/counter1 ? tcnt1 this 8-bit register contains the value of timer/counter1. timer/counter1 is realized as an up counter with read and write access. due to syn- chronization of the cpu, timer/counter1 data written into timer/counter1 is delayed by one cpu clock cycle in synchronous mode and at most two cpu clock cycles for asyn- chronous mode. timer/counter1 output compare registera ? ocr1a the output compare register a is an 8-bit read/write register. the timer/counter output compare register a contains data to be continuously com- pared with timer/counter1. actions on com pare matches are specified in tccr1a. a compare match does only occur if timer/counter1 counts to the ocr1a value. a soft- table 34. timer/counter1 prescale select cs13 cs12 cs11 cs10 description asynchronous mode description synchronous mode 0000timer/counter1 is stopped.timer/c ounter1 is stopped. 0001pck ck 0010pck/2 ck/2 0011pck/4 ck/4 0100pck/8 ck/8 0101pck/16 ck/16 0110pck/32 ck/32 0111pck/64 ck/64 1000pck/128 ck/128 1001pck/256 ck/256 1010pck/512 ck/512 1011pck/ 1024 ck/1024 1100pck/ 2048 ck/2048 1101pck/ 4096 ck/4096 1110pck/ 8192 ck/8192 1111pck/ 16384 ck/16384 bit 76543210 $2e ($4e) msb lsb tcnt1 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 $2d ($4d) msb lsb ocr1a read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 75 attiny26(l) 1477i?avr?10/06 ware write that sets tcnt1 and ocr1a to the same value does not generate a compare match. a compare match will set the compare interrupt flag ocf1a after a synchronization delay following the compare event. timer/counter1 output compare registerb ? ocr1b the output compare register b is an 8-bit read/write register. the timer/counter output compare register b contains data to be continuously com- pared with timer/counter1. actions on com pare matches are specified in tccr1a. a compare match does only occur if timer/counter1 counts to the ocr1b value. a soft- ware write that sets tcnt1 and ocr1b to the same value does not generate a compare match. a compare match will set the compare interrupt flag ocf1b after a synchronization delay following the compare event. timer/counter1 output compare registerc ? ocr1c the output compare register c is an 8-bit read/write register. the timer/counter output compare register c contains data to be continuously com- pared with timer/counter1. a compare match does only occur if timer/counter1 counts to the ocr1c value. a software write that sets tcnt1 and ocr1c to the same value does not generate a compare match. if the ctc1 bit in tccr1b is set, a compare match will clear tcnt1 and set an over- flow interrupt flag (tov1). the flag is set after a synchronization delay following the compare event. this register has the same function in normal mode and pwm mode. pll control and status register ? pllcsr ? bit 7..3 ? res: reserved bits these bits are reserved bits in the attiny26(l) and always read as zero. ? bit 2 ? pcke: pck enable the pcke bit change the timer/counter1 clock source. when it is set, the asynchro- nous clock mode is enabled and fast 64 mhz pck clock is used as timer/counter1 clock source. if this bit is cleared, t he synchronous clock mode is enabled, and system clock ck is used as timer/counter1 clock sour ce. this bit can be set only if plle bit is set. it is safe to set this bit only when the pll is locked i.e., the plock bit is 1. ? bit 1 ? plle: pll enable bit 76543210 $2c ($4c) msb lsb ocr1b read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 $2b ($4b) msb lsb ocr1c read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 $29 ($29) ?????pckeplleplockpllcsr read/write r r r r r r/w r/w r initial value 0 0 0 0 0 0 0/1 0 76 attiny26(l) 1477i?avr?10/06 when the plle is set, the pll is started a nd if needed internal rc oscillator is started as a pll reference clock. if pll is selected as a system clock source the value for this bit is always 1. ? bit 0 ? plock: pll lock detector when the plock bit is set, the pll is locked to the reference clock, and it is safe to enable pck for timer/counter1. after the p ll is enabled, it takes about 64 s/100 s (typical/worst case) for the pll to lock. timer/counter1 initialization for asynchronous mode to change timer/counter1 to the asynchronous mode, first enable pll, and poll the plock bit until it is set, and then set the pcke bit. timer/counter1 in pwm mode when the pwm mode is selected, timer/counter1 and the output compare register c ? ocr1c form a dual 8-bit, free-running and glitch-free pwm generator with outputs on the pb1(oc1a) and pb3(oc1b) pins. also inverted, non-overlapping outputs are avail- able on pins pb0(oc1a ) and pb2(oc1b ), respectively. the non-overlapping output pairs (oc1a - oc1a and oc1b - oc1b ) are never both set at the same time. this allows driving power switches directly. t he non-overlap time is one prescaled clock cycle, and the high time is one cycle shorter than the low time. the non-overlap time is generated by delaying the rising edge, i.e., the positive edge is one prescaled and one pck cycle delayed and the negative edge is one pck cycle delayed in the asynchronous mode. in the synchronous mode he positive edge is one prescaled and one ck cycle delayed and the negative edge is one ck cycle delayed. the high time is also one prescaled cycle shorter in the both operation modes. figure 41. the non-overlapping output pair when the counter value match the contents of ocr1a and ocr1b, the oc1a and oc1b outputs are set or cleared according to the com1a1/com1a0 or com1b1/com1b0 bits in the timer/counter1 control register a ? tccr1a, as shown in table 35 below. timer/counter1 acts as an up-counter, counting from $00 up to the value specified in the output compare register (ocr1c), and starting from $00 up again. a compare match with oc1c will set an overflow inte rrupt flag (tov1) af ter a synchronization delay following the compare event. oc1x oc1x x = a or b t non-overlap 77 attiny26(l) 1477i?avr?10/06 note that in pwm mode, wr iting to the output compare registers ocr1a or ocr1b, the data value is first transferred to a temporary location. the value is latched into ocr1a or ocr1b when the timer/counter reaches ocr1c. this prevents the occur- rence of odd-length pwm pulses (glitches) in the event of an unsynchronized ocr1a or ocr1b. see figure 42 for an example. figure 42. effects of unsynchronized ocr latching during the time between the write and the latch operation, a read from ocr1a or ocr1b will read the contents of the temporary location. this means that the most recently written value always will read out of ocr1a or ocr1b. when ocr1a or ocr1b contain $00 or the top value, as specified in ocr1c register, the output pb1(oc1a) or pb3(oc1b) is held low or high according to the settings of com1a1/com1a0. this is shown in table 36. table 35. compare mode select in pwm mode com1x1 com1x0 effect on output compare pins 00 oc1x not connected. oc1x not connected. 01 oc1x cleared on compare match. set when tcnt1 = $01. oc1x set one prescaled cycle after compare match. cleared when tcnt1 = $00. 10 oc1x cleared on compare match. set when tcnt1 = $01. oc1x not connected. 11 oc1x set one prescaled cycle after compare match. cleared when tcnt = $00 oc1x not connected. pwm output oc1x pwm output oc1x unsynchronized oc1x latch synchronized oc1x latch counter value compare value counter value compare value compare value changes glitch compare value changes 78 attiny26(l) 1477i?avr?10/06 in pwm mode, the timer overflow flag ? tov1, is set as in normal timer/counter mode. timer overflow interrupt1 operates exactly as in normal timer/counter mode, i.e., it is executed when tov1 is set provided that timer overflow interrupt and global interrupts are enabled. this also applies to the timer output compare flags and interrupts. the frequency of the pw m will be timer clock 1 frequency divided by (ocr1c value + 1). see the following equation: resolution shows how many bit is required to express the value in the ocr1c register. it is calculated by following equation resolution pwm = log 2 (ocr1c + 1) table 36. pwm outputs ocr1x = $00 or ocr1c, x = a or b com1x1 com1x0 ocr1x output oc1x output oc1x 0 1 $00 l h 0 1 ocr1c h l 1 0 $00 l not connected 1 0 ocr1c h not connected 1 1 $00 h not connected 1 1 ocr1c l not connected f pwm f tck1 ocr1c + 1 () ----------------------------------- - = 79 attiny26(l) 1477i?avr?10/06 table 37. timer/counter1 clock prescale select in the asynchronous mode pwm frequency (khz) clock selectio n cs13..cs10 ocr1c resolution (bits) 20 pck/16 0101 199 7.6 30 pck/16 0101 132 7.1 40 pck/8 0100 199 7.6 50 pck/8 0100 159 7.3 60 pck/8 0100 132 7.1 70 pck/4 0011 228 7.8 80 pck/4 0011 199 7.6 90 pck/4 0011 177 7.5 100 pck/4 0011 159 7.3 110 pck/4 0011 144 7.2 120 pck/4 0011 132 7.1 130 pck/2 0010 245 7.9 140 pck/2 0010 228 7.8 150 pck/2 0010 212 7.7 160 pck/2 0010 199 7.6 170 pck/2 0010 187 7.6 180 pck/2 0010 177 7.5 190 pck/2 0010 167 7.4 200 pck/2 0010 159 7.3 250 pck 0001 255 8.0 300 pck 0001 212 7.7 350 pck 0001 182 7.5 400 pck 0001 159 7.3 450 pck 0001 141 7.1 500 pck 0001 127 7.0 80 attiny26(l) 1477i?avr?10/06 watchdog timer the watchdog timer is clocke d from a separate on-chip oscillator which runs at 1 mhz. this is the typical value at v cc = 5v. see characterization data for typical values at other v cc levels. by controlling the watchdog timer presca ler, the watchdog reset interval can be adjusted from 16 to 2048 ms. the wdr ? watchdog reset ? instruction resets the watchdog timer. eight different clock cycle periods can be selected to deter- mine the reset period. if the reset period expires without another watchdog reset, the attiny26(l) resets and executes from the reset vector. for timing details on the watch- dog reset, refer to page 36. to prevent unintentional disabling of the watchdog, a special turn-off sequence must be followed when the watchdog is disabled. refer to the description of the watchdog timer control register for details. figure 43. watchdog timer watchdog timer control register ? wdtcr ? bits 7..5 ? res: reserved bits these bits are reserved bits in the attiny26(l) and will always read as zero. ? bit 4 ? wdce: watchdog change enable this bit must be set when the wde bit is written to logic zero. otherwise, the watchdog will not be disabled. once written to one, har dware will clear this bit after four clock cycles. refer to the description of the wde bit for a watchdog disable procedure. in safety level 1 and 2, this bit must also be set when changing the prescaler bits. ? bit 3 ? wde: watchdog enable when the wde is set (one) the watchdog timer is enabled, and if the wde is cleared (zero) the watchdog timer function is di sabled. wde can be cleared only when the wdce bit is set(one). to disable an enabl ed watchdog timer, the following procedure must be followed: normally 1 mhz watchdog presclaler watchdog reset wdp0 wdp1 wdp2 wde mcu reset bit 765 4 3210 $21 ($41) ? ? ? wdce wde wdp2 wdp1 wdp0 wdtcr read/write r r r r/w r/w r/w r/w r/w initial value000 0 0000 81 attiny26(l) 1477i?avr?10/06 1. in the same operation, write a logical one to wdce and wde. a logical one must be written to wde even though it is set to one before the disable operation starts. 2. within the next four clock cycles, write a logical 0 to wde. this disables the watchdog. ? bits 2..0 ? wdp2, wdp1, wdp0: watchdog timer prescaler 2, 1, and 0 the wdp2, wdp1 and wdp0 bits determine the watchdog timer prescaling when the watchdog timer is enabled. the different prescaling values and their corresponding time-out periods are shown in table 38. note: 1. the frequency of the watchdog oscill ator is voltage dependent. the wdr ? watch- dog reset ? instruction should always be executed before the watchdog timer is enabled. this ensures that the reset peri od will be in accordance with the watchdog timer prescale settings. if the watchdog timer is enabled without reset, the watch- dog timer may not start counting from zero. table 38. watchdog timer prescale select (1) wdp2 wdp1 wdp0 number of wdt oscillator cycles typical time-out at v cc = 3.0v typical time-out at v cc = 5.0v 0 0 0 16k (16,384) 17.1 ms 16.3 ms 0 0 1 32k (32,768) 34.3 ms 32.5 ms 0 1 0 64k (65,536) 68.5 ms 65 ms 0 1 1 128k (131,072) 0.14 s 0.13 s 1 0 0 256k (262,144) 0.27 s 0.26 s 1 0 1 512k (524,288) 0.55 s 0.52 s 1 1 0 1,024k (1,048,576) 1.1 s 1.0 s 1 1 1 2,048k (2,097,152) 2.2 s 2.1 s 82 attiny26(l) 1477i?avr?10/06 universal serial interface ? usi the universal serial interface, or usi, provides the basic hardware resources needed for serial communication. combined with a minimum of control software, the usi allows significantly higher transfer rates and uses less code space than solutions based on software only. interrupts are included to minimize the processor load. the main features of the usi are: ? two-wire synchronous data tr ansfer (master or slave, f sclmax = f ck /16) ? three-wire synchronous data transfer (master, f sckmax = f ck /2, slave f sckmax = f ck /4) ? data received interrupt ? wakeup from idle mode ? in two-wire mode: wake-up from all sl eep modes, including power-down mode ? two-wire start condition detector with interrupt capability overview a simplified block diagram of the usi is shown on figure 44. figure 44. universal serial inte rface, block diagram the 8-bit shift register is directly accessi ble via the data bus and contains the incoming and outgoing data. the register has no buffering so the data must be read as quickly as possible to ensure that no data is lost. the mo st significant bit is connected to one of two output pins depending of the wire mode config uration. a transparent latch is inserted between the serial register output and output pin, which delays the change of data out- put to the opposite clock edge of the data input sampling. the serial input is always sampled from the data input (di) pin independent of the configuration. the 4-bit counter can be both read and written via the data bus, and can generate an overflow interrupt. both the serial regi ster and the counter are clocked simultaneously by the same clock source. this allows the counter to count the number of bits received or transmitted and generate an interrupt when the transfer is complete. note that when an external clock source is selected the c ounter counts both clock edges. in this case the counter counts the number of edges, and not the number of bits. the clock can be selected from three different sources: the sck pin, timer 0 overflow, or from software. the two-wire clock control unit can generate an interrupt when a start condition is detected on the two-wire bus. it can also gener ate wait states by holding the clock pin low after a start condition is detected, or after the counter overflows. data bus usipf usitc usiclk usics0 usics1 usioif usioie usidc usisif usiwm0 usiwm1 usisie bit7 two-wire clock control unit pb0 pb1 pb2 do (output only) di/sda (input/open drain) sck/scl (input/open drain) 4-bit counter usidr usisr dq le usicr clock hold tim0 ovf bit0 [1] 3 0 1 2 3 0 1 2 0 1 2 83 attiny26(l) 1477i?avr?10/06 register descriptions usi data register ? usidr the usi uses no buffering of the serial regi ster, i.e., when accessing the data register (usidr) the serial register is accessed direct ly. if a serial clock occurs at the same cycle the register is written, the re gister will contain the value writ ten and no shift is performed. a (left) shift operation is performed depending of the usics1..0 bits setting. the shift operation can be controlled by an external clock edge, by a timer/counter0 overflow, or directly by software using the usiclk str obe bit. note that even when no wire mode is selected (usiwm1..0 = 0) both the external data input (di/sda) and the external clock input (sck/scl) can still be used by the shift register. the output pin in use, do or sda depending on the wire mode, is connected via the out- put latch to the most significant bit (bit 7) of the data register. the output latch is open (transparent) during the first half of a serial clock cycle when an external clock source is selected (usics1 = 1), and constantly open when an internal cl ock source is used (usics1 = 0). the output will be changed imme diately when a new msb written as long as the latch is open. the latch ensures t hat data input is sampled and data output is changed on opposite clock edges. note that the corresponding data direction register (ddrb2/1) to the pin must be set to one for enabling data output from the shift register. usi status register ? usisr the status register contains interrupt flags, line status flags and the counter value. note that doing a read-modify-write operation on usisr register, i.e., using the sbi or cbi instructions, will clear pending interrupt flags. it is recommended that register con- tents is altered by using the out instruction only. ? bit 7 ? usisif: start condition interrupt flag when two-wire mode is selected, the usisif flag is set (to one) when a start condition is detected. when output disable mode or three-wire mode is selected and (usicsx = 0b11 & usiclk = 0) or (usics = 0b10 & usiclk = 0), any edge on the sck pin sets the flag. an interrupt will be generated wh en the flag is set while the usisie bit in usicr and the global interrupt enable flag are set. the fl ag will only be cleared by writing a logical one to the usisif bit. clearing th is bit will release the start dete ction hold of scl in two-wire mode. a start condition interrupt will wakeup the processor from all four sleep modes. ? bit 6 ? usioif: counter overflow interrupt flag this flag is set (one) when the 4-bit counter overflows (i.e., at the transition from 15 to 0). an interrupt will be generated when the flag is set while the usioie bit in usicr and the global interrupt enable fl ag are set. the flag will only be cleared if a one is written bit 7 6 5 4 3 2 1 0 $0f ($2f) msb lsb usidr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543 210 $0e ($2e) usisif usioif usipf usidc usicnt3 usicnt2 usicnt1 usicnt0 usisr read/write r/w r/w r/w r r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 84 attiny26(l) 1477i?avr?10/06 to the usioif bit. clearing this bit will releas e the counter overflow hold of scl in two- wire mode. a counter overflow interrupt will wakeup the processor from idle sleep mode. ? bit 5 ? usipf: stop condition flag when two-wire mode is selected, the usipf flag is set (one) when a stop condition is detected. the flag is cleared by writing a one to this bit. note that this is not an interrupt flag. this signal is useful when implem enting two-wire bus master arbitration. ? bit 4 ? usidc: data output collision this bit is logical one when bit 7 in the shift register differs from the physical pin value. the flag is only valid when two-wire mode is used. this signal is useful when imple- menting two-wire bus master arbitration. ? bits 3..0 ? usicnt3..0: counter value these bits reflect the current 4-bit counter va lue. the 4-bit counter value can directly be read or written by the cpu. the 4-bit counter increments by one for each clock generated either by the external clock edge detector, by a timer/counter0 ov erflow, or by software using usiclk or usitc strobe bits. the clock source depends of the setting of the usics1..0 bits. for external clock operation a special feature is added that allows the clock to be generated by writing to the usitc strobe bit. this feature is enabled by write a one to the usiclk bit while setting an external clock source (usics1 = 1). note that even when no wire mode is selected (usiwm1..0 = 0) the external clock input (sck/scl) are can still be used by the counter. usi control register ? usicr the control register includes interrupt enable control, wire mode setting, clock select setting, and clock strobe. ? bit 7 ? usisie: start condition interrupt enable setting this bit to one enables the start condition detector interrupt. if there is a pending interrupt when the usisie and the global interrupt enable flag is set to one, this will immediately be executed. refer to the description of ?bit 7 ? usisif: start condition interrupt flag? on page 83 for further details. when two-wire mode is selected, the usisif flag is set (to one) when a start condition is detected. when output disable mode or three-wire mode is selected and (usicsx = 0b11 & usiclk = 0) or (usics = 0b10 & usiclk = 0), any edge on the sck pin sets the flag. ? bit 6 ? usioie: counter overflow interrupt enable setting this bit to one enables the counter overflow interrupt. if there is a pending inter- rupt when the usioie and the global interrupt enable flag is set to one, this will immediately be executed. refer to the description of ?bit 6 ? usioif: counter overflow interrupt flag? on page 83 for further details. bit 7 6 5 4 3 2 1 0 $0d ($2d) usisie usioie usiwm1 usiwm0 us ics1 usics0 usiclk usitc usicr read/write r/w r/w r/w r/w r/w r/w w w initial value 0 0 0 0 0 0 0 0 85 attiny26(l) 1477i?avr?10/06 ? bit 5..4 ? usiwm1..0: wire mode these bits set the type of wire mode to be used. basically only the function of the outputs are affected by these bits. data and clock inputs are not affected by the mode selected and will always have the same func tion. the counter and shift register can therefore be clocked externally, and data input sampled, even when outputs are disabled. the relations between usiwm1..0 and the usi operation is summarized in table 39. when two-wire mode is selected, the usisif flag is set (to one) when a start condition is detected. when output disable mode or three-wire mode is selected and (usicsx = 0b11 & usiclk = 0) or (usics = 0b10 & usiclk = 0), any edge on the sck pin sets the flag. note: 1. the di and sck pins are renamed to serial data (sda) and serial clock (scl) respectively to avoid confusion between the modes of operation. table 39. relations between usiwm1..0 and the usi operation usiwm1 usiwm0 description 0 0 outputs, clock hold, and start detector disabled. port pins operates as normal. 0 1 three-wire mode. uses do, di, and sck pins. the data output (do) pin overrides the portb1 bit in the portb register in this mode. however, the corresponding ddrb1 bit still controls the data direction. when the port pin is set as input (ddrb1 = 0) the pins pull-up is controlled by the portb1 bit. the data input (di) and serial clock (sck) pins do not affect the normal port operation. when operating as master, clock pulses are software generated by toggling the portb2 bit while ddrb2 is set to output. the usitc bit in the usi cr register can be used for this purpose. 1 0 two-wire mode. uses sda (di) and scl (sck) pins (1) . the serial data (sda) and the serial clock (scl) pins are bi- directional and uses open-collector output drives. the output drivers are enabled by the ddrb0/2 bit in the ddrb register. when the output driver is enabled fo r the sda pin, the output driver will force the line sda low if the output of the shift register or the portb0 bit in the portb register is zero. otherwise the sda line will not be driven (i.e., it is released). when the scl pin output driver is enabled the scl line will be forced low if the portb2 bit in the portb register is zero, or by the start detector. otherwise the scl line will not be driven. the scl line is held low when a start detector detects a start condition and the output is enabled. clearing the start condition flag (usisif) releases the line. the sda and scl pin inputs is not affected by enabling this mode. pull-ups on the sda and scl port pin are disabled in two-wire mode. 1 1 two-wire mode. uses sda and scl pins. same operation as for the two-wire mode described above, except that the scl line is also held low when a counter overflow occurs, and is held low until the counter overflow flag (usioif) is cleared. 86 attiny26(l) 1477i?avr?10/06 ? bit 3..2 ? usics1..0: clock source select these bits set the clock source for the shift register and counter. the data output latch ensures that the output is changed at the opposite edge of the sampling of the data input (di/sda) when using external clock source (sck/scl). when software strobe or timer0 overflow clock option is selected the output latch is transparent and therefore the output is changed immediately. clearing the usics1..0 bits enables software strobe option. when using this option, writing a on e to the usiclk bit clocks both the shift register and the counter. for external cloc k source (usics1 = 1), the usiclk bit is no longer used as a strobe, but selects between external clocking, and software clocking by the usitc strobe bit. table 40 shows the relationship between the usics1..0 and usiclk setting and clock source used for the shift register and the 4-bit counter. ? bit 1 ? usiclk: clock strobe writing a one to this bit location strobes the shift register to shift one step and the counter to increment by one provided that the usics1..0 bits are set to zero and by doing so selects the software clock strobe option. the output will change immediately when the clock strobe is executed i.e. in the same instruction cycle. the value shifted into the shift register is sampled the previous instruction cycle. the bit will be read as zero. when an external clock source is selected (usics1 = 1), the usiclk function is changed from a clock strobe to a clock select register. setting the usiclk bit in this case will select the usitc strobe bit as clock source for the 4-bit counter (see table 40). ? bit 0 ? usitc: toggle clock port pin writing a one to this bit location toggles the portb2 (sck/scl) value from either from 0 to 1, or 1 to 0. the toggling is inde pendent of the ddrb2 setting, but if the portb2 value is to be shown on the pin the ddrb2 must be set as output (to one). this feature allows easy clock generation when implemen ting master devices. the bit will be read as zero. when an external clock source is selected (usics1 = 1) and the usiclk bit is set to one, writing to the usitc str obe bit will directly clock the 4-bit counter. th is allows an early detection of when the transfer is done when operating as a master device. table 40. relations between the usics1..0 and usiclk setting usics1 usics0 usiclk shift register clock source 4-bit counter clock source 0 0 0 no clock no clock 0 0 1 software clock strobe (usiclk) software clock strobe (usiclk) 0 1 x timer/counter0 overflow timer/counter0 overflow 1 0 0 external, positive edge external, both edges 1 1 0 external, negative edge external, both edges 1 0 1 external, positive edge software clock strobe (usitc) 1 1 1 external, negative edge software clock strobe (usitc) 87 attiny26(l) 1477i?avr?10/06 functional descriptions three-wire mode the usi three-wire mode is compliant to the serial peripheral interface (spi) mode 0 and 1, but does not have the slave select (ss) pin functionality. however, this feature can be implemented in software if necessary. pin names used by this mode are: di, do, and sck. figure 45. three-wire mode operation, simplified diagram figure 45 shows two usi units operating in three-wire mode, one as master and one as slave. the two shift registers are interconnected in such way that after eight sck clocks, the data in each register are interchanged. the same clock also increments the usi?s 4-bit counter. the counter overflow (interrupt) flag, or usioif, can therefore be used to determine when a transfer is completed. the clock is generated by the master device software by toggling the pb2 pin via the portb register or by writing a one to the usitc bit in usicr. figure 46. three-wire mode, timing diagram the three-wire mode timing is shown in figure 46. at the top of the figure is a sck cycle reference. one bit is shifted into the usi shift register (usidr) for each of these cycles. the sck timing is shown for both ex ternal clock modes. in external clock mode 0 (usics0 = 0), di is sampled at positiv e edges, and do is changed (data register is slave master bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 pby pbx pbz do di sck bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 pby pbx pbz do di sck portbz msb msb 654321lsb 1 2 3 4 5 6 7 8 654321lsb sck sck do di d c b a e cycle ( reference ) 88 attiny26(l) 1477i?avr?10/06 shifted by one) at negative edges. external clock mode 1 (usics0 = 1) uses the oppo- site edges versus mode 0, i.e., samples data at negative and changes the output at positive edges. the usi clock modes corresponds to the spi data mode 0 and 1. referring to the timing diagram (figure 46.), a bus transfer involves the following steps: 1. the slave device and master device sets up its data output and, depending on the protocol used, enables its output driver (mark a and b). the output is set up by writing the data to be transmitted to the serial data register. enabling of the output is done by setting the corresponding bit in the port data direction register (ddrb2). note that point a and b does not have any specific order, but both must be at least one half sck cycle before point c where the data is sampled. this must be done to ensure that the data setup requirement is satisfied. the 4- bit counter is reset to zero. 2. the master generates a clock pulse by software toggling the sck line twice (c and d). the bit value on the slave and master?s data input (di) pin is sampled by the usi on the first edge (c), and the data output is changed on the opposite edge (d). the 4-bit counter will count both edges. 3. step 2. is repeated eight times for a comlpete register (byte) transfer. 4. after eight clock pulses (i .e., 16 clock edges) the coun ter will overflow and indi- cate that the transfer is completed. the data bytes transferred must now be processed before a new transfer can be in itiated. the overflow interrupt will wake up the processor if it is set to idle mode. depending of the protocol used the slave device can now set its output to high impedance. spi master operation example the following code demonstrates how to use the usi module as a spi master: spitransfer: out usidr,r16 ldi r16,(1< 91 attiny26(l) 1477i?avr?10/06 figure 48. two-wire mode, typical timing diagram referring to the timing diagram (figure 48.), a bus transfer involves the following steps: 1. the a start condition is generated by th e master by forcing the sda low line while the scl line is high (a). sda can be forced low either by writing a zero to bit 7 of the shift register, or by setting the po rtb0 bit to zero. note that ddrb0 must be set to one for the output to be enabled. the slave device?s start detector logic (figure 49.) detects the start condition and sets the usisif flag. the flag can generate an interrupt if necessary. 2. in addition, the start detector will hold the scl line low after the master has forced an negative edge on this line (b). this allows the slave to wake up from sleep or complete its other tasks, before setting up the shift register to receive the address by clearing the start condition flag and reset the counter. 3. the master set the first bit to be transferred and releases the scl line (c). the slave samples the data and shift it into the serial register at the positive edge of the scl clock. 4. after eight bits are transferred containing slave address and data direction (read or write), the slave counter overflows and the scl line is forced low (d). if the slave is not the one the master has addressed it releases the scl line and waits for a new start condition. 5. if the slave is addressed it holds the sda line low during the acknowledgment cycle before holding the scl line low again (i.e., the counter register must be set to 14 before releasing scl at (d)). depending of the r/w bit the master or slave enables its output. if the bit is set, a master read operation is in progress (i.e., the slave drives the sda line) the slave can hold the scl line low after the acknowledge (e). 6. multiple bytes can now be transmitted, a ll in same direction, until a stop condition is given by the master (f). or a new start condition is given. if the slave is not able to receive more data it does not acknowledge the data byte it has last received. when the master does a read operation it must terminate the operation by force the acknowledge bit low after the last byte transmitted. figure 49. start condition detector, logic diagram p s address 1 - 7 8 9 r/w ack ack 1 - 8 9 data ack 1 - 8 9 data sda scl a b d e c f sda scl write( usisif) clock hold usisif dq clr dq clr 92 attiny26(l) 1477i?avr?10/06 start condition detector the start condition detector is shown in figure 49. the sda line is delayed (in the range of 50 to 300 ns) to ensure valid sampling of the scl line. the start condition detector is only enabled in two-wire mode. when two-wire mode is selected, the usisif flag is set (to one) when a start condition is detected. when output disable mode or three-wire mode is selected and (usicsx = 0b11 & usiclk = 0) or (usics = 0b10 & usiclk = 0), any edge on the sck pin sets the flag. the start condition detector is working asynchronously and can therefore wake up the processor from the power-down sleep mode. however, the protocol used might have restrictions on the scl hold time. therefore, when using this feature in this case the oscillator start-up time set by the cksel fu ses (see ?clock systems and their distribu- tion? on page 24) must also be taken into the consideration. refer to the description of ?bit 7 ? usisif: start condition interrupt flag? on page 83 for further details. alternative usi usage when the usi unit is not used for serial communication, it can be set up to do alternative tasks due to its flexible design. half-duplex asynchronous data transfer by utilizing the shift register in three-wire mode, it is possible to implement a more compact and higher performance uart than by software only. 4-bit counter the 4-bit counter can be used as a stand-alone counter with overflow interrupt. note that if the counter is clocked externally , both clock edges will generate an increment. 12-bit timer/counter combining the usi 4-bit counter and timer/counter0 allows them to be used as a 12-bit counter. edge triggered external interrupt by setting the counter to maximum value (f ) it can function as an additional external interrupt. the overflow flag and interrupt ena ble bit are then used for the external inter- rupt. this feature is selected by the usics1 bit. software interrupt the counter overflow interrupt can be used as a software interrupt triggered by a clock strobe. 93 attiny26(l) 1477i?avr?10/06 analog comparator the analog comparator compares the input values on the positive pin pa6 (ain0) and negative pin pa7 (ain1). when the voltage on the positive pin pa6 (ain0) is higher than the voltage on the negative pin pa7 (ain1), the analog comparator output, aco is set (one). the comparator?s output can trigger a separate interrupt, exclusive to the analog comparator. the user can select interrupt triggering on comparator output rise, fall or toggle. a block diagram of the comparator and its surrounding logic is shown in the fig- ure 50. figure 50. analog comparator block diagram analog comparator control and status register ? acsr ? bit 7 ? acd: analog comparator disable when this bit is set(one), the power to the a nalog comparator is switched off. this bit can be set at any time to turn off the analog comparator. when changing the acd bit, the analog comparator interrupt must be disabled by clearing the acie bit in acsr. otherwise an interrupt can occur when the bit is changed. ? bit 6 ? acbg: analog comparator bandgap select when this bit is set (one), it selects internal bandgap reference voltage (1.18v) as the positive comparator input. ? bit 5 ? aco: analog comparator output aco is directly connected to the comparator output. pa6 (ain0) pa7 mux mux mux adc multiplexer output (ain1) acbg acme bit 76543210 $08 ($28) acd acbg aco aci acie acme acis1 acis0 acsr read/write r/w r/w r r/w r/w r/w r/w r/w initial value 0 0 x 0 0 0 0 0 94 attiny26(l) 1477i?avr?10/06 ? bit 4 ? aci: analog comparator interrupt flag this bit is set (one) when a comparator output event triggers the interrupt mode defined by aci1 and aci0. the analog comparator in terrupt routine is executed if the acie bit is set (one) and the i-bit in sreg is set (one ). aci is cleared by hardware when execut- ing the corresponding interrupt handling vector. alternatively, aci is cleared by writing a logic one to the flag. ? bit 3 ? acie: analog comparator interrupt enable when the acie bit is set (one) and the i-bit in the status register is set (one), the ana- log comparator interrupt is activated. when cleared (zero), the interrupt is disabled. ? bit 2 ? acme: analog comparator multiplexer enable when the acme bit is set (one) and the adc is switched off (aden in adcsr is zero), mux3...0 in admux select the input pin to replace the negative input to the analog comparator, as shown in table 42 on page 95. if acme is cleared (zero) or aden is set (one), pa7(ain1) is applied to the negative input to the analog comparator. ? bits 1, 0 ? acis1, acis0: analog comparator interrupt mode select these bits determine which comparator events that trigger the analog comparator inter- rupt. the different settings are shown in table 41. note: 1. when changing the acis1/acis0 bits, the analog comparator interrupt must be dis- abled by clearing its interrupt enable bit in the acsr register. otherwise an interrupt can occur when the bits are changed. table 41. acis1/acis0 settings (1) acis1 acis0 interrupt mode 0 0 comparator interrupt on output toggle 01reserved 1 0 comparator interrupt on falling output edge 1 1 comparator interrupt on rising output edge 95 attiny26(l) 1477i?avr?10/06 notes: 1. mux4 does not affect analog comparator input selection. 2. pin change interrupt on pa6 and pa7 is disabled if the analog comparator is enabled. this happens regardless of whet her ain1 or ain0 has been replaced as inputs to the analog comparator. 3. the mux3...0 selections go into effect after one clock cycle delay. table 42. analog comparator input selection (1) acme aden mux3...0 (3) analog comparator negative input 0 x xxxx ain1 1 1 xxxx ain1 1 0 0000 adc0 1 0 0001 adc1 1 0 0010 adc2 1 0 0011 adc3 1 0 0100 adc4 1 0 0101 adc5 1 0 0110 adc6 (2) 1 0 0111 adc7 (2) 1 0 1000 adc8 1 0 1001 adc9 1 0 1010 adc10 1 0 1011 undefined 1 0 1100 undefined 1 0 1101 undefined 1 0 1110 undefined 1 0 1111 undefined 96 attiny26(l) 1477i?avr?10/06 analog to digital converter features ? 10-bit resolution ? 2 lsb absolute accuracy ? 0.5 lsb integral non-linearity ? optional offset cancellation ? 13 - 260 s conversion time ? 11 multiplexed single ended input channels ? 8 differential input channels ? 7 differential input channels with optional gain of 20x ? optional left adjustment for adc result readout ? 0 - avcc adc input voltage range ? selectable adc reference voltage ? free running or single conversion mode ? interrupt on adc co nversion complete ? sleep mode noise canceler the attiny26(l) features a 10-bit successive approximation adc. the adc is con- nected to an 11-channel analog multiplexer which allows eight differential voltage input combinations or 11 single-ended voltage inputs constructed from seven pins from port a and four pins from port b. seven of the differential inputs are equipped with a program- mable gain stage, providing amplification st eps of 0 db (1x) and 26 db (20x) on the differential input voltage before the a/d conversion. there are four groups of three dif- ferential analog input channel selections. all input channels in each group share a common negative terminal, while another adc input can be selected as the positive input terminal. the single-ended voltage inputs refer to 0v (gnd). the adc contains a sample and hold amplifier which ensures that the input voltage to the adc is held at a constant level during conversion. a block diagram of the adc is shown in figure 51. the adc has an analog supply voltage pin, avcc. the voltage on avcc must not differ more than 0.3v from v cc . see the paragraph ?adc noise canceling techniques? on page 107 on how to connect these pins. an internal reference voltage of nominally 2. 56v is provided on-chip, and this reference may be externally decoupled at the aref pin by a capacitor. 97 attiny26(l) 1477i?avr?10/06 figure 51. analog to digital converter block schematic operation the adc converts an analog input voltage to a 10-bit digital value through successive approximation. the minimum value represents gnd and the maximum value represents the voltage on the aref pin minus 1 lsb. optionally, avcc or and internal 2.56v refer- ence voltage may be connected to the aref pin by writing to the refs bits in admux. the internal voltage reference may thus be decoupled by an external capacitor at the aref pin to improve noise immunity. the analog input channel and differential gain are selected by writing to the mux bits in admux. any of the 11 adc input pins adc10..0, as well as gnd and a fixed bandgap voltage reference of nominally 1.18v (v bg ), can be selected as single ended inputs to the adc. a selection of adc input pins can be selected as positive and negative inputs to the differential gain amplifier. if differential channels are selected, the differential gain stage amplifies the voltage dif- ference between the selected input channel pair by the selected gain factor. note that the voltage on the positive input terminal must be higher than on the negative input ter- adc conversion complete irq 8-bit data bus 15 0 adc multiplexer select (admux) adc ctrl. & status register (adcsr) adc data register (adch/adcl) mux2 adie adfr adsc aden adif adif mux1 mux0 adps0 adps1 adps2 mux3 conversion logic 10-bit dac + - sample & hold comparator mux decoder mux4 adc7 adc6 adc5 adc4 adc3 adc2 adc1 adc0 refs0 refs1 adlar + - channel selection gain selection adc[9:0] adc multiplexer output gain amplifier internal 1.18 v reference prescaler single ended / differential selection gnd pos. input mux neg. input mux adc10 adc9 adc8 internal 2.56 v reference vcc aref 98 attiny26(l) 1477i?avr?10/06 minal, otherwise the gain stage will saturate at 0v (gnd). this amplified value then becomes the analog input to the adc. if single ended channels are used, the gain amplifier is bypassed altogether. the adc can operate in two modes ? single conversion and free running mode. in single conversion mode, each conversion will have to be initiated by the user. in free running mode, the adc is constantly samp ling and updating the adc data register. the adfr bit in adcsr selects between the two available modes. the adc is enabled by setting the adc enable bit, aden in adcsr. voltage reference and input channel select ions will not go into effect until aden is set. the adc does not consume power when aden is cleared, so it is recommended to switch off the adc before entering power saving sleep modes. a conversion is started by writing a logical one to the adc start conversion bit, adsc. this bit stays high as long as the conversion is in prog ress and will be set to zero by hardware when the conversion is completed. if a different data channel is selected while a conversion is in progress, the adc will fi nish the current conver sion before performing the channel change. the adc generates a 10-bit result, which is presented in the adc data registers, adch and adcl. by default, the result is presented right adjusted, but can optionally be presented left adjusted by setting the adlar bit in admux. if the result is left adjusted and no more than 8-bit precision is requir ed, it is sufficient to read adch. otherwise, adcl must be read fi rst, then adch, to en sure that the content of the data registers belongs to the same conversion. once adcl is read, adc access to data registers is blocked. this means that if adcl has been read, and a conversion completes before adch is read, neither register is updated and the result from the con- version is lost. when adch is read, adc access to the adch and adcl registers is re-enabled. the adc has its own interrupt which can be triggered when a conversion completes. when adc access to the data registers is prohibited between reading of adch and adcl, the interrupt will trigger even if t he result is lost. prescaling and conversion timing figure 52. adc prescaler 7-bit adc prescaler adc clock source ck adps0 adps1 adps2 ck/128 ck/2 ck/4 ck/8 ck/16 ck/32 ck/64 reset aden 99 attiny26(l) 1477i?avr?10/06 the successive approximation circuitry requires an input clock frequency between 50 khz and 200 khz. if a lower resolution than 10 bits is needed, the input clock fre- quency to the adc can be as high as 1000 khz to get a higher sample rate. the adc module contains a prescaler, which divides the system clock to an acceptable adc clock frequency. the adps bits in adcsr are used to generate a proper adc clock input frequency from any chip clock frequency above 100 khz. the prescaler starts counting from the moment the adc is switched on by setting the aden bit in adcsr. the prescaler keeps running for as long as the aden bit is set, and is continuously reset when aden is low. when initiating a conversion by setting the ad sc bit in adcsr, the conversion starts at the following rising edge of the adc clock cycle. if differential channels are selected, the conversion will only start at every other rising edge of the adc clock cycle after aden was set. a normal conversion takes 13 adc clock cycle s. in certain situations, the adc needs more clock cycles to initialization and minimi ze offset errors. extended conversions take 25 adc clock cycles and occur as the first conversi on after the adc is switched on (aden in adcsr is set). special care should be taken when changing differential channels. once a differential channel has been selected, the gain stage may take as much as 125 s to stabilize to the new value. thus conversions should not be started within the first 125 s after selecting a new differential channel. alternatively, conversions results obtained within this period should be discarded. the same settling time should be observed for the first differential conversion after changing adc reference (by changing the refs1:0 bits in admux). the actual sample-and-hold takes place 1.5 adc clock cycles after the start of a normal conversion and 13.5 adc clock cycles after the start of an extended conversion. when a conversion is complete, the result is written to the adc data registers, and adif is set. in single conversion mode, adsc is cleared simultaneously. the software may then set adsc again, and a new conversion will be initiated on the fi rst rising adc clock edge. in free running mode, a new conversion will be started immediately after the conversion completes, while adsc remains high. using free running mode and an adc clock frequency of 200 khz gives the lowest conversion time, 65 s , equivalent to 15 ksps. for a summ ary of conversion ti mes, see table 43. figure 53. adc timing diagram, extended conversion (single conversion mode) msb of result lsb of result adc clock adsc sample & hold adif adch adcl cycle number aden 1 212 13 14 15 16 17 18 19 20 21 22 23 24 25 1 2 extended conversion next conversion 3 mux and refs update mux and refs update conversion complete 100 attiny26(l) 1477i?avr?10/06 figure 54. adc timing diagram, single conversion figure 55. adc timing diagram, free running conversion changing channel or reference selection the muxn and refs1:0 bits in the admux register are single buffered through a tem- porary register to which the cpu has random access. this ensures that the channels and reference selection only takes place at a safe point during the conversion. the channel and reference selection is continuously updated until a conversion is started. once the conversion starts, the channel and reference selection is locked to ensure a sufficient sampling time for the adc. c ontinuous updating resumes in the last adc clock cycle before the conversion completes (a dif in adcsr is set). note that the con- version starts on the following rising adc clock edge after adsc is written. the user is thus advised not to write new channel or reference selection values to admux until one adc clock cycle after adsc is written. table 43. adc conversion time condition sample & hold (cycles from start of conversion) conversion time (cycles) conversion time (s) extended conversion 13.5 25 125 - 500 normal conversions 1.5 13 65 - 260 1 2 3 4 5 6 7 8 9 10 11 12 13 msb of result lsb of result adc clock adsc adif adch adcl cycle number 12 one conversion next conversion 3 sample & hold mux and refs update conversion complete mux and refs update 11 12 13 msb of result lsb of result adc clock adsc adif adch adcl cycle number 12 one conversion next conversion 34 conversion complete sample & hold mux and refs update 101 attiny26(l) 1477i?avr?10/06 special care should be taken when changing differential channels. once a differential channel has been selected, the gain sta ge may take as much as 125 s to stabilize to the new value. thus conversions should not be started within the first 125 s after selecting a new differential channel. alternatively, conversion results obtained within this period should be discarded. the same settling time should be observed for the first differential conversion after changing adc reference (by changi ng the refs1:0 bits in admux). adc noise canceler function the adc features a noise canceler that enables conversion during adc noise reduc- tion mode (see ?power management and sl eep modes? on page 38) to reduce noise induced from the cpu core and other i/o peripherals. if other i/o peripherals must be active during conversion, this mode works equivalently for idle mode. to make use of this feature, the following procedure should be used: 1. make sure that the adc is enabled and is not busy converting. single conver- sion mode must be selected and the adc conversion complete interrupt must be enabled. aden = 1 adsc = 0 adfr = 0 adie = 1 2. enter adc noise reduction mode (or idle mode). the adc will start a conver- sion once the cpu has been halted. 3. if no other interrupts occur before the adc conversion completes, the adc inter- rupt will wake up the cpu and execute t he adc conversion complete interrupt routine. adc conversion result after the conversion is complete (adif is high), the conversion result can be found in the adc result registers (adcl, adch). for single ended conversion, the result is where v in is the voltage on the selected input pin and v ref the selected voltage refer- ence (see table 45 on page 103 and table 46 on page 104). 0x000 represents analog ground, and 0x3ff represents the selected reference voltage minus one lsb. if differential channels are used, the result is where v pos is the voltage on the positive input pin, v neg the voltage on the negative input pin, gain the selected gain factor, and v ref the selected voltage reference. keep in mind that v pos must be higher than v neg , otherwise, the adc value will saturate at 0x000. figure 56 shows the decoding of the differential input range. table 44 shows the resulting output codes if the differential input channel pair (adcn - adcm) is selected with a gain of gain and a reference voltage of v ref . adc v in 1024 ? v ref -------------------------- = adc v pos v neg ? () gain 1024 ?? v ref --------------------------------------------------------------------------- = 102 attiny26(l) 1477i?avr?10/06 figure 56. differential measurement range example: admux = 0xeb (adc0 - adc1, 20x gain, 2.56v reference, left adjusted result) voltage on adc0 is 400 mv, voltage on adc1 is 300 mv. adcr = 1024 * 20 * (400 - 300) / 2560 = 800 = 0x320 adcl will thus read 0x00, and adch will read 0xc8. writing zero to adlar right adjusts the result: adcl = 0x20, adch = 0x03. table 44. correlation between input voltage and output codes v adcn read code corresponding decimal value v adcm + v ref /gain 0x3ff 1023 v adcm + (1023/1024) v ref /gain 0x3ff 1023 v adcm + (1022/1024) v ref /gain 0x3fe 1022 ... ... ... v adcm + (1/1024) v ref /gain 0x001 1 v adcm 0x000 0 0 output code 0x3ff 0x000 v ref /gain differential input voltage (volts) 103 attiny26(l) 1477i?avr?10/06 adc multiplexer selection register ? admux ? bit 7, 6 ? refs1, refs0: reference selection bits these bits select the voltage reference for the adc, as shown in table 45. if these bits are changed during a co nversion, the change will not go in effect until this conversion is complete (adif in adcsr is set). the user should disregard the first conversion result after changing these bits to obtain maximum accuracy. if differential channels are used, using avcc or an external aref higher than (avcc - 0.2v) is not recommended, as this will affect adc accuracy. the internal voltage reference may not be used if an external reference voltage is being applied to the aref pin. ? bit 5 ? adlar: adc left adjust result the adlar bit affects the presentation of the adc conversion result in the adc data register. if adlar is cleared, the result is right adjusted. if adlar is set, the result is left adjusted. changing the adlar bit will affect the adc data register immediately, regardless of any ongoing conversions. for a complete description of this bit, see ?adc data register ? adcl and adch? on page 106. ? bits 4..0 ? mux4..mux0: analog channel and gain selection bits the value of these bits selects which combination of analog inputs are connected to the adc. these bits also select the gain for the differential channels. see table 46 for details. if these bits are changed during a conv ersion, the change will not go in effect until this conversion is comp lete (adif in adcsr is set). bit 76543210 $07 ($27) refs1 refs0 adlar mux4 mux3 mux2 mux1 mux0 admux read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 table 45. voltage reference selections for adc refs1 refs0 voltage reference selection 00avcc 0 1 aref (pa3), internal vref turned off. 1 0 internal voltage reference (2.56 v), aref pin (pa3) not connected. 11 internal voltage reference (2.56 v) with external capacitor at aref pin (pa3). 104 attiny26(l) 1477i?avr?10/06 note: 1. for offset measurements only. se e ?offset compensation schemes? on page 107. table 46. input channel and gain selections mux4..0 single ended input positive differential input negative differential input gain 00000 adc0 n/a 00001 adc1 00010 adc2 00011 adc3 00100 adc4 00101 adc5 00110 adc6 00111 adc7 01000 adc8 01001 adc9 01010 adc10 01011 n/a adc0 adc1 20x 01100 adc0 adc1 1x 01101 (1) adc1 adc1 20x 01110 adc2 adc1 20x 01111 adc2 adc1 1x 10000 n/a adc2 adc3 1x 10001 (1) adc3 adc3 20x 10010 adc4 adc3 20x 10011 adc4 adc3 1x 10100 n/a adc4 adc5 20x 10101 adc4 adc5 1x 10110 (1) adc5 adc5 20x 10111 adc6 adc5 20x 11000 adc6 adc5 1x 11001 n/a adc8 adc9 20x 11010 adc8 adc9 1x 11011 (1) adc9 adc9 20x 11100 adc10 adc9 20x 11101 adc10 adc9 1x 11110 1.18v (v bg ) n/a 11111 0v (gnd) 105 attiny26(l) 1477i?avr?10/06 adc control and status register ? adcsr ? bit 7 ? aden: adc enable writing a logical ?1? to this bit enables the ad c. by clearing this bit to zero, the adc is turned off. turning the adc off while a conversion is in progress, will terminate this conversion. ? bit 6 ? adsc: adc start conversion in single conversion mode, a logical ?1? must be written to this bit to start each conver- sion. in free running mode, a logical ?1? must be written to this bit to start the first conversion. the first time adsc has been wr itten after the adc has been enabled, or if adsc is written at the same time as t he adc is enabled, a dummy conversion will pre- cede the initiated conversion. this dummy co nversion performs init ialization of the adc. adsc will read as one as long as a conversion is in progress. when the conversion is complete, it returns to zero. when a dummy conversion precedes a real conversion, adsc will stay high until the real conversion completes. writing a 0 to this bit has no effect. ? bit 5 ? adfr: adc free running select when this bit is set (one) the adc operates in free running mode. in this mode, the adc samples and updates the data registers continuously. clearing this bit (zero) will terminate free running mode. ? bit 4 ? adif: adc interrupt flag this bit is set (one) when an adc conversion completes and the data registers are updated. the adc conversion complete interrupt is executed if the adie bit and the i- bit in sreg are set (one). adif is clea red by hardware when executing the correspond- ing interrupt handling vector. alternatively, adif is cleared by writing a logical one to the flag. beware that if doing a read-modify-write on adcsr, a pending interrupt can be dis- abled. this also applies if the sbi and cbi instructions are used. ? bit 3 ? adie: adc interrupt enable when this bit is set (one) and the i-bit in sreg is set (one), the adc conversion com- plete interrupt is activated. bit 76543210 $06 ($26) aden adsc adfr adif adie adps2 adps1 adps0 adcsr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 106 attiny26(l) 1477i?avr?10/06 ? bits 2..0 ? adps2..0: adc prescaler select bits these bits determine the division factor between the ck frequency and the input clock to the adc. adc data register ? adcl and adch adlar = 0 adlar = 1 when an adc conversion is complete, the resu lt is found in these two registers. the adlar bit in admux affect the way the result is read from the registers. if adlar is set, the result is left adjusted. if adlar is cleared (default), the result is right adjusted. if the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read adch. otherwise, adcl must be read first, then adch. ? adc9..0: adc conversion result these bits represent the result from the conversion. for differential channels, this is the absolute value after gain adjustment, as indicated in table 46 on page 104. for single ended channels, $000 represents analog ground, and $3ff represents the selected ref- erence voltage minus one lsb. table 47. adc prescaler selections adps2 adps1 adps0 division factor 000 2 001 2 010 4 011 8 100 16 101 32 110 64 1 1 1 128 bit 151413121110 9 8 $05 ($25) ? ? ? ? ? ? adc9 adc8 adch $04 ($24) adc7 adc6 adc5 adc4 adc3 adc2 adc1 adc0 adcl 76543210 read/writerrrrrrrr rrrrrrrr initial value00000000 00000000 bit 151413121110 9 8 $05 ($25) adc9 adc8 adc7 adc6 adc5 adc4 adc3 adc2 adch $04 ($24) adc1 adc0 ? ????? adcl 76543210 read/writerrrrrrrr rrrrrrrr initial value00000000 00000000 107 attiny26(l) 1477i?avr?10/06 scanning multiple channels since change of analog channel always is delayed until a conversion is finished, the free running mode can be used to scan multiple channels without interrupting the con- verter. typically, the adc conversion complete interrupt will be used to perform the channel shift. however, the user should take the following fact into consideration: the interrupt triggers once the result is ready to be read. in free running mode, the next conversioin will start immediately when the interr upt triggers. if admux is changed after the interrupt triggers, the next conversion has already started, and the old setting is used. adc noise canceling techniques digital circuitry inside and outside the attiny26(l) generates emi which might affect the accuracy of analog measurements. if conversion accuracy is critical, the noise level can be reduced by applying the following techniques: 1. the analog part of the attiny26(l) and all analog components in the application should have a separate analog ground plane on the pcb. this ground plane is connected to the digital ground plane via a single point on the pcb. 2. keep analog signal paths as short as possible. make sure analog tracks run over the analog ground plane, and keep them well away from high-speed switching digital tracks. 3. the avcc pin on the attiny26(l) should be connected to the digital v cc supply voltage via an lc network as shown in figure 57. 4. use the adc noise canceler function to reduce induced noise from the cpu. 5. if some pins are used as digital outputs, it is essential that these do not switch while a conversion is in progress in that port. offset compensation schemes the gain stage has a built-in offset cancellation circuitry that nulls the offset of differen- tial measurements as much as possible. the remaining offset in the analog path can be measured directly by selecting the same channe l for both differential inputs. this offset residue can be then subtracted in software from the measurement results. using this kind of software based offset correction, offset on any channel can be reduced below one lsb. 108 attiny26(l) 1477i?avr?10/06 figure 57. adc power connections pa0 (adc0) (adc10/reset) pb7 (adc9/int0/t0) pb6 (adc8/xtal2) pb5 (adc7/xtal1) pb4 vcc pa1 (adc1) pa2 (adc2) pa3 (aref) pa4 (adc3) pa5 (adc4) pa6 (adc5/ain0) pa7 (adc6/ain1) gnd avcc 10 ? 100nf analog ground plane attiny26/l 20 20 6 5 7 8 9 gnd 10 16 14 13 12 11 18 19 15 17 1 3 2 4 (mosi/di/sda/oc1a) pb0 (miso/do/oc1a) pb1 (sck/scl/oc1b) pb2 (oc1b) pb3 109 attiny26(l) 1477i?avr?10/06 memory programming program and data memory lock bits the attiny26 provides two lock bits which can be left unprogrammed (?1?) or can be programmed (?0?) to obtain the additional features listed in table 49. the lock bits can only be erased to ?1? with the chip erase command. note: 1. ?1? means unprogrammed, ?0? means programmed notes: 1. program the fuse bits before programming the lock bits. 2. ?1? means unprogrammed, ?0? means programmed table 48. lock bit byte (1) lock bit byte bit no description default value 7 ? 1 (unprogrammed) 6 ? 1 (unprogrammed) 5 ? 1 (unprogrammed) 4 ? 1 (unprogrammed) 3 ? 1 (unprogrammed) 2 ? 1 (unprogrammed) lb2 1 lock bit 1 (unprogrammed) lb1 0 lock bit 1 (unprogrammed) table 49. lock bit protection modes memory lock bits protection type lb mode lb2 (2) lb1 (2) 1 1 1 no memory lock features enabled. 210 further programming of the flash and eeprom is disabled in parallel and serial programming mode. the fuse bits are locked in both serial and parallel programming mode. (1) 300 further programming and verification of the flash and eeprom is disabled in parallel and serial programming mode. the fuse bits are locked in both serial and parallel programming mode. (1) 110 attiny26(l) 1477i?avr?10/06 fuse bits the attiny26 has two fuse bytes. table 50 and table 51 describe briefly the functional- ity of all the fuses and how they are mapped into the fuse bytes. note that the fuses are read as logical zero, ?0?, if they are programmed. notes: 1. the spien fuse is not accessible in serial programming mode. 2. when programming the rstdisbl fuse, parallel programming has to be used to change fuses or perform further programming. notes: 1. the default value of sut1..0 results in maximum start-up time. see table 12 on page 30 for details. 2. the default setting of cksel3..0 results in internal rc oscillator at 1 mhz. see table 3 on page 26 for details. 3. the ckopt fuse functionality depends on the setting of the cksel bits. see ?sys- tem clock and clock options? on page 24 for details. the status of the fuse bits is not affected by chip erase. note that the fuse bits are locked if lock bit1 (lb1) is programmed. program the fuse bits before programming the lock bits. table 50. fuse high byte fuse high byte bit no de scription default value 7 ? 1 (unprogrammed) 6 ? 1 (unprogrammed) 5 ? 1 (unprogrammed) rstdisbl (2) 4 select if pb7 is i/o pin or reset pin 1 (unprogrammed, pb7 is reset pin) spien (1) 3 enable serial program and data downloading 0 (programmed, spi prog. enabled) eesave 2 eeprom memory is preserved through the chip erase 1 (unprogrammed, eeprom not preserved) bodlevel 1 brown out detector trigger level 1 (unprogrammed) boden 0 brown out detector enable 1 (unprogrammed, bod disabled) table 51. fuse low byte fuse low byte bit no description default value pllck 7 use pll for internal clock 1 (unprogrammed) ckopt (3) 6 oscillator options 1 (unprogrammed) sut1 5 select start-up time 1 (unprogrammed) (1) sut0 4 select start-up time 0 (programmed) (1) cksel3 3 select clock source 0 (programmed) (2) cksel2 2 select clock source 0 (programmed) (2) cksel1 1 select clock source 0 (programmed) (2) cksel0 0 select clock source 1 (unprogrammed) (2) 111 attiny26(l) 1477i?avr?10/06 latching of fuses the fuse values are latched when the device enters programming mode and changes of the fuse values will have no effect until th e part leaves progra mming mode. this does not apply to the eesave fuse which will take effect once it is programmed. the fuses are also latched on power-up in normal mode. signature bytes all atmel microcontrollers have a three-byte signature code which identifies the device. this code can be read in both serial and parallel mode, also when the device is locked. the three bytes reside in a separate address space. for the attiny26 the signature bytes are: 1. $000: $1e (indicates manufactured by atmel). 2. $001: $91 (indicates 2kb flash memory). 3. $002: $09 (indicates attiny26 device when $001 is $91). calibration byte the attiny26 stores four differe nt calibration values for the internal rc oscillator. these bytes resides in the signature row high byte of the addresses 0x0000, 0x0001, 0x0002, and 0x0003 for 1, 2, 4, and 8 mhz respectively. during reset, the 1 mhz value is auto- matically loaded into the osccal register. if other frequencies are used, the calibration value has to be loaded manually, see ?o scillator calibration register ? osc- cal? on page 30 for details. page size parallel programming parameters, pin mapping, and commands this section describes how to parallel program and verify flash program memory, eeprom data memory, memory lock bits, and fuse bits in the attiny26. pulses are assumed to be at least 250 ns unless otherwise noted. signal names in this section, some pins of the attiny26 are referenced by signal names describing their functionality during parallel programming, see figure 58 and table 54. pins not described in the following table are referenced by pin names. the xa1/xa0 pins determine the action executed when the xtal1 pin is given a posi- tive pulse. the bit coding is shown in table 56. when pulsing wr or oe , the command loaded determines the action executed. the dif- ferent commands are shown in table 57. table 52. no. of words in a page and no. of pages in the flash flash size page size pcword no. of pages pcpage pcmsb 1k words (2k bytes) 16 words pc[3:0] 64 pc[9:4] 9 table 53. no. of words in a page and no. of pages in the eeprom eeprom size page size pcword no. of pages pcpage eeamsb 128 bytes 4 bytes eea[1:0] 32 eea[7:0] 7 112 attiny26(l) 1477i?avr?10/06 figure 58. parallel programming note: 1. the pin is used for two different contro l signals. in the description below, normally only one of the signals is referred. e.g., ?give bs1 a positive pulse? equals ?give pagel/bs1 a positive pulse?. table 54. pin name mapping signal name in programming mode pin name i/o function wr pb0 i write pulse (active low) xa0 pb1 i xtal action bit 0 xa1/bs2 (1) pb2 i xtal action bit 1 multiple xed with byte select 2 (?0? selects low byte, ?1? selects 2?nd high byte) pagel/bs1 (1) pb3 i program memory and eeprom data page load multiplexed with byte select 1 (?0? selects low byte, ?1? selects high byte). oe pb5 i output enable (active low) rdy/bsy pb6 o 0: device is busy programming, 1: device is ready for new command data pa7:0 i/o bidirectional data bus (output when oe is low) table 55. pin values used to enter programming mode pin symbol value pagel/bs1 prog_enable[3] 0 xa1/bs2 prog_enable[2] 0 xa0 prog_enable[1] 0 wr prog_enable[0] 0 vcc +5v gnd xtal1/pb4 pb0 pb1 pb2 pb3 pb5 pa7: pa0 data reset pb6 +12 v xa0 oe rdy/bsy pagel/bs1 wr xa1/bs2 avcc +5v 113 attiny26(l) 1477i?avr?10/06 note: 1. [xa1, xa0] = 0b11 is ?no action, idle?. as long as xtal1 is not pulsed, the com- mand, address, and data registers rema in unchanged. therefore, there are no problems using bs2 as described below even though bs2 is multiplexed with xa1. bs2 is only asserted when reading the fuses (oe is low) and xtal1 is not pulsed. table 56. xa1 and xa0 coding (1) xa1 xa0 action when xtal1 is pulsed 00 load flash or eeprom address (high or low address byte determined by bs1). 0 1 load data (high or low data byte for flash determined by bs1). 1 0 load command 1 1 no action, idle table 57. command byte bit coding command byte command executed 1000 0000 chip erase 0100 0000 write fuse bits 0010 0000 write lock bits 0001 0000 write flash 0001 0001 write eeprom 0000 1000 read signature bytes and calibration byte 0000 0100 read fuse and lock bits 0000 0010 read flash 0000 0011 read eeprom 114 attiny26(l) 1477i?avr?10/06 parallel programming enter programming mode the following algorithm puts the device in parallel programming mode: step 2-7 must be completed within 64ms. 1. set prog_enable pins listed in table 55 on page 112, reset and vcc to 0v. 2. apply 4.5 - 5.5v between vcc/avcc and gnd. 3. wait at least 60us. 4. apply between 4.5v - 5.5v (sam e as on vcc/avcc) to reset pin. 5. wait at least 20us. 6. apply between 11.5v - 12.5v to reset pin. 7. wait at least 10us. 8. program fuses to internal clock mode, 8 mhz, with 64ms delay. (cksel[3..0] = 0100, sut[1..0] = 10). if lock bits are programmed, a chip erase command must be executed before changing the fuses. 9. exit programming mode by power the device down or by bringing reset pin to 0v. 10. repeat step 1 to 7 too re-enter programming mode. considerations for efficient programming the loaded command and address are retained in the device during programming. for efficient programming, the following should be considered. ? the command needs only be loaded once when writing or reading multiple memory locations. ? skip writing the data value $ff, that is the contents of the en tire eeprom (unless the eesave fuse is programmed) and flash after a chip erase. ? address high byte needs only be loaded before programming or reading a new 256- word window in flash or 256-byte eeprom . this consideration also applies to signature bytes reading. 115 attiny26(l) 1477i?avr?10/06 chip erase the chip erase will er ase the flash and eeprom (1) memories plus lock bits. the lock bits are not reset until the program memory has been completely erased. the fuse bits are not changed. a chip erase must be performed before the flash and/or eeprom are reprogrammed. note: 1. the eeprom memory is preserved during chip erase if the eesave fuse is programmed. load command ?chip erase? 1. set xa1, xa0 to ?10?. this enables command loading. 2. set bs1 to ?0?. 3. set data to ?1000 0000?. this is the command for chip erase. 4. give xtal1 a positive pulse. this loads the command. 5. give wr a negative pulse. this starts the chip erase. rdy/bsy goes low. 6. wait until rdy/bsy goes high before loading a new command. programming the flash the flash is organized in pages, see tabl e 52 on page 111. when programming the flash, the program data is latched into a page buffer. this allows one page of program data to be programmed simultaneously. the following procedure describes how to pro- gram the entire flash memory: a. load command "write flash" 1. set xa1, xa0 to ?10?. this enables command loading. 2. set bs1 to ?0?. 3. set data to ?0001 0000?. this is the command for write flash. 4. give xtal1 a positive pulse. this loads the command. b. load address low byte 1. set xa1, xa0 to ?00?. this enables address loading. 2. set bs1 to ?0?. this selects low address. 3. set data = address low byte ($00 - $ff). 4. give xtal1 a positive pulse. this loads the address low byte. c. load data low byte 1. set xa1, xa0 to ?01?. this enables data loading. 2. set data = data low byte ($00 - $ff). 3. give xtal1 a positive pulse. this loads the data byte. d. load data high byte 1. set bs1 to ?1?. this selects high data byte. 2. set xa1, xa0 to ?01?. this enables data loading. 3. set data = data high byte ($00 - $ff). 4. give xtal1 a positive pulse. this loads the data byte. e. repeat b through d until the entire buffer is filled or unt il all data within the page is loaded. while the lower bits in the address are mapped to words within the page, the higher bits address the pages within the flash. this is illustrated in figure 59 on page 116. note that if less than 8 bits are required to address words in the page (pagesize < 256), the most significant bit(s) in the address low byte are used to address the page when per- forming a page write. 116 attiny26(l) 1477i?avr?10/06 f. load address high byte 1. set xa1, xa0 to ?00?. this enables address loading. 2. set bs1 to ?1?. this selects high address. 3. set data = address high byte ($00 - $03). 4. give xtal1 a positive pulse. this loads the address high byte. g. program page 1. set bs1 to ?0?. 2. give wr a negative pulse. this starts programming of the entire page of data. rdy/bsy goes low. 3. wait until rdy/bsy goes high. (see figure 60 for signal waveforms.) h. repeat b through g until the entire flash is programmed or until all data has been programmed. i. end page programming 1. set xa1, xa0 to ?10?. this enables command loading. 2. set data to ?0000 0000?. this is the command for no operation. 3. give xtal1 a positive pulse. this loads the command, and the internal write sig- nals are reset. figure 59. addressing the flash which is organized in pages (1) note: 1. pcpage and pcword are listed in table 52 on page 111. program memory word address within a page page address within the flash instruction word pag e pcword[pagemsb:0]: 00 01 02 pageend pag e pcword pcpage pcmsb pagemsb program counter 117 attiny26(l) 1477i?avr?10/06 figure 60. programming the flash waveforms (1) note: 1. ?xx? is don?t care. the letters re fer to the programming description above. programming the eeprom the eeprom is organized in pages, see table 53 on page 111. when programming the eeprom, the program data is latched into a page buffer . this allows one page of data to be programmed simultaneously. the programming algorithm for the eeprom data memory is as follows (refer to ?programming the flash? on page 115 for details on command, address and data loading): 1. a: load command ?0001 0001?. 2. b: load address low byte ($00 - $ff). 3. c: load data ($00 - $ff). j: repeat 2 and 3 until the entire buffer is filled k: program eeprom page 1. set bs1 to ?0?. 2. give wr a negative pulse. this starts programming of the eeprom page. rdy/bsy goes low. 3. wait until to rdy/bsy goes high before programming the next page. (see figure 61 for signal waveforms.) rdy/bsy wr oe reset +12v $10 addr. low addr. high data data low data high addr. low data low data high xa1/bs2 xa0 pagel/bs1 xtal1 xx ab cdb cd fg e 118 attiny26(l) 1477i?avr?10/06 figure 61. programming the eeprom waveforms reading the flash the algorithm for reading the flash memory is as follows (refer to ?programming the flash? on page 115 for details on command and address loading): 1. a: load command ?0000 0010?. 2. f: load address high byte ($00 - $03). 3. b: load address low byte ($00 - $ff). 4. set oe to ?0?, and bs1 to ?0?. the flash word low byte can now be read at data. 5. set bs1 to ?1?. the flash word high byte can now be read at data. 6. set oe to ?1?. reading the eeprom the algorithm for readi ng the eeprom memory is as follows (refer to ?programming the flash? on page 115 for details on command and address loading): 1. a: load command ?0000 0011?. 2. b: load address low byte ($00 - $ff). 3. set oe to ?0?, and bs1 to ?0?. the eeprom data byte can now be read at data. 4. set oe to ?1?. programming the fuse low bits the algorithm for programming the fuse low bits is as follows (refer to ?programming the flash? on page 115 for details on command and data loading): 1. a: load command ?0100 0000?. 2. c: load data low byte. bit n = ?0? programs and bit n = ?1? erases the fuse bit. 3. set bs1 and bs2 to ?0?. 4. give wr a negative pulse and wait for rdy/bsy to go high. $11 addr. low data addr. low data xx ab c b c k j rdy/bsy wr oe reset +12v data xa1/bs2 xa0 pagel/bs1 xtal1 119 attiny26(l) 1477i?avr?10/06 programming the fuse high bits the algorithm for programming the fuse high bits is as follows (refer to ?programming the flash? on page 115 for details on command and data loading): 1. a: load command ?0100 0000?. 2. c: load data low byte. bit n = ?0? programs and bit n = ?1? erases the fuse bit. 3. set bs1 to ?1? and bs2 to ?0?. this selects high data byte. 4. give wr a negative pulse and wait for rdy/bsy to go high. 5. set bs1 to ?0?. this selects low data byte. figure 62. programming the fuse waveforms programming the lock bits the algorithm for programming the lock bits is as follows (refer to ?programming the flash? on page 115 for details on command and data loading): 1. a: load command ?0010 0000?. 2. c: load data low byte. bit n = ?0? programs the lock bit. 3. give wr a negative pulse and wait for rdy/bsy to go high. the lock bits can only be cleared by executing chip erase. reading the fuse and lock bits the algorithm for reading the fuse and lock bits is as follows (refer to ?programming the flash? on page 115 for details on command loading): 1. a: load command ?0000 0100?. 2. set oe to ?0?, bs2 to ?0?, and bs1 to ?0?. the status of the fuse low bits can now be read at data (?0? means programmed). 3. set oe to ?0?, bs2 to ?1?, and bs1 to ?1?. the status of the fuse high bits can now be read at data (?0? means programmed). 4. set oe to ?0?, bs2 to ?0?, and bs1 to ?1?. the status of the lock bits can now be read at data (?0? means programmed). 5. set oe to ?1?. rdy/bsy wr oe reset +12v $40 data data xx xa1/bs2 xa0 pagel/bs1 xtal1 ac $40 data xx ac write fuse low byte write fuse high byte 120 attiny26(l) 1477i?avr?10/06 figure 63. mapping between bs1, bs2 and the fuse- and lock-bits during read reading the signature bytes the algorithm for reading the signature bytes is as follows (refer to programming the flash for details on command and address loading): 1. a: load command ?0000 1000?. 2. b: load address low byte ($00 - $02). 3. set oe to ?0? and bs1 to ?0?. the selected signature byte can now be read at data. 4. set oe to ?1?. reading the calibration byte the algorithm for reading the calibration byte is as follows (refer to programming the flash for details on command and address loading): 1. a: load command ?0000 1000?. 2. b: load address low byte. 3. set oe to ?0? and bs1 to ?1?. the calibration byte can now be read at data. 4. set oe to ?1?. parallel programming characteristics figure 64. parallel programming timing, including some general timing requirements fuse low byte lock bits 0 1 bs2 fuse high byte 0 1 bs1 data data & contol (data, xa0, xa1/bs2 pagel/bs1) xtal1 t xhxl t wlwh t dvxh t xldx t wlrh wr rdy/bsy t xlwl t wlbx t bvwl wlrl 121 attiny26(l) 1477i?avr?10/06 figure 65. parallel programming timing, loading sequence with timing requirements (1) note: 1. the timing requirements shown in figure 64 (i.e., t dvxh , t xhxl , and t xldx ) also apply to loading operation. figure 66. parallel programming timing, reading sequence (within the same page) with timing requirements () note: 1. the timing requirements shown in figure 64 (i.e. t dvxh , t xhxl , and t xldx ) also apply to reading operation. xtal1 pagel/bs1 xlxh t addr0 (low byte) data (low byte) data (high byte) addr1 (low byte) data xa0 xa1/bs2 load address (low byte) load data (low byte) load data (high byte) load address (low byte) xlxh t xlxh t xtal1 oe addr0 (low byte) data (low byte) data (high byte) addr1 (low byte) data pagel/bs1 xa0 xa1/bs2 load address (low byte) read data (low byte) read data (high byte) load address (low byte) t bhdv t oldv t xlol t ohdz 122 attiny26(l) 1477i?avr?10/06 notes: 1. t wlrh is valid for the write flash, write eeprom, write fuse bits and write lock bits commands. 2. t wlrh_ce is valid for the chip erase command. table 58. parallel programming characteristics, v cc = 5v 10% symbol parameter min typ max units v pp programming enable voltage 11.5 12.5 v i pp programming enable current 250 a t dvxh data and control valid before xtal1 high 67 ns t xlxh xtal1 low to xtal1 high 200 ns t xhxl xtal1 pulse width high 150 ns t xldx data and control hold after xtal1 low 67 ns t xlwl xtal1 low to wr low 0 ns t wlbx bs2/1 hold after wr low 67 ns t bvwl bs1 valid to wr low 67 ns t wlwh wr pulse width low 150 ns t wlrl wr low to rdy/bsy low 0 1 s t wlrh wr low to rdy/bsy high (1) 3.7 4.5 ms t wlrh_ce wr low to rdy/bsy high for chip erase (2) 7.5 9 ms t xlol xtal1 low to oe low 0 ns t bvdv bs1 valid to data valid 0 250 ns t oldv oe low to data valid 250 ns t ohdz oe high to data tri-stated 250 ns 123 attiny26(l) 1477i?avr?10/06 serial downloading both the flash and eeprom memory arrays can be programmed using the serial spi bus while reset is pulled to gnd. the serial interface consists of pins sck, mosi (input) and miso (o utput). after reset is set low, the programming enable instruction needs to be executed first before program/ erase operations can be executed. note, in table 59 on page 123, the pin mapping for spi programming is listed. not all parts use the spi pins dedicated for the internal spi interface. note that throughout the descrip- tion about serial downloading, mosi and miso are used to describe the serial data in and serial data out respectively. serial programming pin mapping figure 67. serial programming and verify (1) notes: 1. if the device is clocked by the internal oscillator, there is no need to connect a clock source to the xtal1 pin. 2. v cc -0.3v < avcc < v cc +0.3v, however, avcc should always be within 2.7 - 5.5v. when programming the eeprom, an auto-erase cy cle is built into the self-timed pro- gramming operation (in the serial mode only) and there is no need to first execute the chip erase instruction. the chip erase operation turns the content of every memory location in both the program and eeprom arrays into $ff. depending on cksel fuses, a valid clock must be present. the minimum low and high periods for the serial clock (sck) input are defined as follows: low: > 2 cpu clock cycles for f ck < 12 mhz, 3 cpu clock cycles for f ck 12 mhz high: > 2 cpu clock cycles for f ck < 12 mhz, 3 cpu clock cycles for f ck 12 mhz table 59. pin mapping serial programming symbol pins i/o description mosi pb0 i serial data in miso pb1 o serial data out sck pb2 i serial clock vcc gnd xtal1 sck miso mosi reset pb0 pb1 pb2 2.7 - 5.5v avcc 2.7 - 5.5v (2) 124 attiny26(l) 1477i?avr?10/06 spi serial programming algorithm when writing serial data to the attiny26, da ta is clocked on the rising edge of sck. when reading data from the attiny26, data is clocked on the falling edge of sck. see figure 68, figure 69, and table 69 for timing details. to program and verify the attiny26 in the serial programming mode, the following sequence is recommended (see four byte instruction formats in table 61 ): 1. power-up sequence: apply power between v cc and gnd while reset and sck are set to ?0?. in some systems, the programmer can not guarantee that sck is held low during power-up. in this case, reset must be given a positive pulse of at least two cpu clock cycles duration after sck has been set to ?0?. 2. wait for at least 20 ms and enable serial programming by sending the program- ming enable serial instruction to pin mosi. 3. the serial programming instructions will not work if the communication is out of synchronization. when in synchronize the second by te ($53), will echo back when issuing the third byte of the programming enable instruction. whether the echo is correct or not, all 4 bytes of the instruction must be transmitted. if the $53 did not echo back, give reset a positive pulse and issue a new programming enable command. 4. the flash is programmed one page at a time. the page size is found in table 52 on page 111. the memory page is loaded one byte at a time by supplying the 4 lsb of the address and data together with the load program memory page instruction. to ensure correct loading of the page, the data low byte must be loaded before data high byte is applied for given address. the program memory page is stored by loading the write program memory page instruction with the 6 msb of the address. if polling is not us ed, the user must wait at least t wd_flash before issuing the next page. (see table 60). accessing the serial programming interface before the flash write operation completes can result in incorrect programming. 5. the eeprom array is programmed one byte at a time by supplying the address and data together with th e appropriate write instru ction. an eeprom memory location is first automatically erased bef ore new data is written. if polling is not used, the user must wait at least t wd_eeprom before issuing the next byte. (see table 60). in a chip erased device, no $ffs in the data file(s) need to be programmed. 6. any memory location can be verified by using the read instruction which returns the content at the selected address at serial output miso. 7. at the end of the programming session, reset can be set high to commence normal operation. 8. power-off sequence (if needed): set reset to ?1?. tu r n v cc power off. 125 attiny26(l) 1477i?avr?10/06 data polling flash when a page is being programmed into the flash, reading an address location within the page being programmed will gi ve the value $ff. at the time the device is ready for a new page, the pr ogrammed value will read correctly. this is used to de termine when the next page can be written. note that the entire page is written simultaneously and any address within the page can be used for polling. data polling of the flash will not work for the value $ff, so when pr ogramming this value, the user will have to wait for at least t wd_flash before programming the next page. as a chip-erased device contains $ff in all locations, programming of addresses that are meant to contain $ff, can be skipped. see table 60 for t wd_flash value. data polling eeprom when a new byte has been written and is being programmed into eeprom, reading the address location being program med will give the value $ff. at the time the device is ready for a new byte, the programmed value will read correctly. this is used to deter- mine when the next byte can be written. this will not work for the value $ff, but the user should have the following in mind: as a chip-erased device contains $ff in all locations, programming of addresses that are meant to contain $ff, can be skipped. this does not apply if the eeprom is re-programmed without chip-erasing the device. in this case, data polling cannot be used for the value $ff, a nd the user will have to wait at least t wd_eeprom before programming the next byte. see table 60 for t wd_eeprom value. figure 68. serial programm ing waveforms table 60. minimum wait delay befo re writing the next fl ash or eeprom location symbol minimum wait delay t wd_flash 4.5 ms t wd_eeprom 9.0 ms t wd_erase 9.0 ms t wd_fuse 4.5 ms msb msb lsb lsb serial clock input (sck) serial data input (mosi) (miso) sample serial data output 126 attiny26(l) 1477i?avr?10/06 note: a = address high bits b = address low bits h = 0 ? low byte, 1 ? high byte o = data out i = data in x = don?t care table 61. serial programming instruction set instruction instruction format operation byte 1 byte 2 byte 3 byte4 programming enable 1010 1100 0101 0011 xxxx xxxx xxxx xxxx enable serial programming after reset goes low. chip erase 1010 1100 100x xxxx xxxx xxxx xxxx xxxx chip erase eeprom and flash. read program memory 0010 h 000 xxxx xx aa bbbb bbbb oooo oooo read h (high or low) data o from program memory at word address a : b . load program memory page 0100 h 000 xxxx xxxx xxxx bbbb iiii iiii write h (high or low) data i to program memory page at word address b . data low byte must be loaded before data high byte is applied within the same address. write program memory page 0100 1100 xxxx xx aa bbbb xxxx xxxx xxxx write program memory page at address a : b . read eeprom memory 1010 0000 xxxx xxxx x bbb bbbb oooo oooo read data o from eeprom memory at address b . write eeprom memory 1100 0000 xxxx xxxx x bbb bbbb iiii iiii write data i to eeprom memory at address b . read lock bits 0101 1000 0000 0000 xxxx xxxx xxxx xxoo read lock bits. ?0? = programmed, ?1? = unprogrammed. see table 48 on page 109 for details. write lock bits 1010 1100 111x xxxx xxxx xxxx 1111 11 ii write lock bits. set bits = ?0? to program lock bits. see table 48 on page 109 for details. read signature byte 0011 0000 xxxx xxxx xxxx xx bb oooo oooo read signature byte o at address b . write fuse bits 1010 1100 1010 0000 xxxx xxxx iiii iiii set bits = ?0? to program, ?1? to unprogram. see table 51 on page 110 for details. write fuse high bits 1010 1100 1010 1000 xxxx xxxx xxx i iiii set bits = ?0? to program, ?1? to unprogram. see table 50 on page 110 for details. read fuse bits 0101 0000 0000 0000 xxxx xxxx oooo oooo read fuse bits. ?0? = programmed, ?1? = unprogrammed. see table 51 on page 110 for details. read fuse high bits 0101 1000 0000 1000 xxxx xxxx xxx o oooo read fuse high bits. ?0? = programmed, ?1? = unprogrammed. see table 50 on page 110 for details. read calibration byte 0011 1000 xxxx xxxx 0000 00 bb oooo oooo read calibration byte o . 127 attiny26(l) 1477i?avr?10/06 serial programming characteristics figure 69. serial programming timing note: 1. 2 t clcl for f ck < 12 mhz, 3 t clcl for f ck >= 12 mhz table 62. serial programming characteristics, t a = -40 c to 85 c, v cc = 2.7v - 5.5v (unless otherwise noted) (1) symbol parameter min typ max units 1/t clcl oscillator frequency (v cc = 2.7 - 5.5 v) 0 8 mhz t clcl oscillator period (v cc = 2.7 - 5.5 v) 125 ns 1/t clcl oscillator frequency (v cc = 4.5 - 5.5 v) 0 16 mhz t clcl oscillator period (v cc = 4.5 - 5.5 v) 62.5 ns t shsl sck pulse width high 2 t clcl (1) ns t slsh sck pulse width low 2 t clcl (1) ns t ovsh mosi setup to sck high t clcl ns t shox mosi hold after sck high 2 t clcl ns t sliv sck low to miso valid 20 ns mosi miso sck t ovsh t shsl t slsh t shox t sliv 128 attiny26(l) 1477i?avr?10/06 electrical characteristics absolute maximum ratings* dc characteristics operating temperature.................................. -55 c to +125 c *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of th is specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. storage temperature ..................................... -65c to +150 c voltage on any pin except reset with respect to ground .............................-0.5v to v cc + 0.5v voltage on reset with respect to ground ....-0.5v to +13.0v maximum operating voltage ............................................ 6.0v dc current per i/o pin ............................................... 40.0 ma dc current v cc and gnd pins ................................ 200.0 ma t a = -40 c to 85 c, v cc = 2.7v to 5.5v (unless otherwise noted) symbol parameter condition min. typ. (1) max. units v il input low voltage except xtal1 pin and reset pins -0.5 0.2v cc v v ih input high voltage except xtal1 and reset pins 0.6v cc (3) v cc +0.5 v v il1 input low voltage xtal1 pin, external clock selected -0.5 0.1v cc v v ih1 input high voltage xtal1 pin, external clock selected 0.8v cc (3) v cc +0.5 v v il2 input low voltage reset pin -0.5 0.2v cc v v ih2 input high voltage reset pin 0.9v cc (3) v cc +0.5 v v il3 input low voltage reset pin as i/o -0.5 0.2v cc v v ih3 input high voltage reset pin as i/o 0.6v cc (3) v cc +0.5 v v ol output low voltage (4) (ports a, b) i ol = 20 ma, v cc = 5v i ol = 10 ma, v cc = 3v 0.7 0.5 v v v oh output high voltage (5) (ports a, b) i oh = -20 ma, v cc = 5v i oh = -10 ma, v cc = 3v 4.2 2.3 v v i il input leakage current i/o pin v cc = 5.5 v, p i n l o w (absolute value) 1a i ih input leakage current i/o pin v cc = 5.5 v, pin high (absolute value) 1a r rst reset pull-up resistor 20 100 k r pu i/o pin pull-up resistor 20 100 k 129 attiny26(l) 1477i?avr?10/06 notes: 1. typical value at 25 c 2. ?max? means the highest value where the pin is guaranteed to be read as low 3. ?min? means the lowest value where t he pin is guaranteed to be read as high 4. although each i/o port can sink more than the test condit ions (20ma at vcc = 5v, 10 ma at vcc = 3v) under steady state conditions (non-transient), th e following must be observed: 1] the sum of all iol, for all ports, should not exceed 400 ma. 2] the sum of all iol, for port a0 - a7, should not exceed 300 ma. 3] the sum of all iol, for ports b0 - b7 should not exceed 300 ma. if iol exceeds the test condition, vol may exceed the related specification. pins are not guar anteed to sink current greater than the listed test condition. 5. although each i/o port can source more than the test conditions (20 ma at v cc = 5v, 10 ma at v cc = 3v) under steady state conditions (non-transient), th e following must be observed: 1] the sum of all ioh, for a ll ports, should not exceed 400 ma. 2] the sum of all ioh, for port a0 - a7, should not exceed 300 ma. 3] the sum of all ioh, for ports b0 - b7 should not exceed 300 ma. if ioh exceeds the test condition, voh may exceed the rela ted specification. pins are not guaranteed to source current greater than the listed test condition. 6. minimum v cc for power-down is 2.5v i cc power supply current active 1 mhz, v cc = 3v ( attiny26 l) 0.70 ma active 4 mhz, v cc = 3v ( attiny26 l) 2.5 6 ma active 8 mhz, v cc = 5v ( attiny26 ) 815ma idle 1 mhz, v cc = 3v ( attiny26 l) 0.18 ma idle 4 mhz, v cc = 3v ( attiny26 l) 0.75 2 ma idle 8 mhz, v cc = 5v ( attiny26 ) 3.5 7 ma power-down mode (6) wdt enabled, v cc = 3v 7.5 15 a wdt disabled, v cc = 3v 0.3 3 a v acio analog comparator input offset voltage v cc = 5v v in = v cc /2 <10 40 mv i aclk analog comparator input leakage current v cc = 5v v in = v cc /2 -50 50 na t acid analog comparator propagation delay v cc = 2.7v v cc = 4.0v 750 500 ns t a = -40 c to 85 c, v cc = 2.7v to 5.5v (unless otherwise noted) (continued) symbol parameter condition min. typ. (1) max. units 130 attiny26(l) 1477i?avr?10/06 external clock drive waveforms figure 70. external clock drive waveforms external clock drive notes: 1. r should be in the range 3 k - 100 k , and c should be at least 20 pf. the c values given in the table includes pin capacitance. this will vary with package type. 2. the frequency will vary with package type and board layout. v il1 v ih1 table 63. external clock drive symbol parameter v cc = 2.7 - 5.5v v cc = 4.5 - 5.5v units min max min max 1/t clcl oscillator frequency 0 8 0 16 mhz t clcl clock period 125 62.5 ns t chcx high time 50 25 ns t clcx low time 50 25 ns t clch rise time 1.6 0.5 s t chcl fall time 1.6 0.5 s t clcl change in period from one clock cycle to the next 22 table 64. external rc oscillator, typical frequencies r [k ] (1) c [pf] f (2) 33 22 650 khz 10 22 2.0 mhz 131 attiny26(l) 1477i?avr?10/06 adc characteristics note: 1. minimum for avcc is 2.7v. 2. maximum for avcc is 5.5v table 65. adc characteristics, si ngle ended channels, t a = -40 c to 85 c symbol parameter condition min typ max units resolution single ended conversion 10 bits absolute accuracy (including inl, dnl, quantization error, gain and offset error) single ended conversion v ref = 4v, v cc = 4v adc clock = 200 khz 1lsb single ended conversion v ref = 4v, v cc = 4v adc clock = 1 mhz 2lsb single ended conversion v ref = 4v, v cc = 4v adc clock = 200 khz noise reduction mode 1lsb single ended conversion v ref = 4v, v cc = 4v adc clock = 1 mhz noise reduction mode 2lsb integral non-linearity (inl) single ended conversion v ref = 4v, v cc = 4v adc clock = 200 khz 0.5 lsb differential non-linearity (dnl) single ended conversion v ref = 4v, v cc = 4v adc clock = 200 khz 0.5 lsb gain error single ended conversion v ref = 4v, v cc = 4v adc clock = 200 khz 0.75 lsb offset error single ended conversion v ref = 4v, v cc = 4v adc clock = 200 khz 0.5 lsb clock frequency 50 1000 khz conversion time 13 260 s avcc analog supply voltage v cc - 0.3 (1) v cc + 0.3 (2) v v ref reference voltage 2.0 avcc v v in input voltage gnd v ref v adc conversion output 0 1023 lsb input bandwidth 38.5 khz v int internal voltage reference 2.4 2.7 2.9 v r ref reference input resistance 32 k r ain analog input resistance 100 m 132 attiny26(l) 1477i?avr?10/06 notes: 1. minimum for avcc is 2.7v. 2. maximum for avcc is 5.5v. table 66. adc characteristics, di fferential channels, t a = -40 c to 85 c symbol parameter condition min typ max units resolution gain = 1x 10 bits gain = 20x 10 bits absolute accuracy gain = 1x v ref = 4v, v cc = 5v adc clock = 50 - 200 khz 24 lsb gain = 20x v ref = 4v, v cc = 5v adc clock = 50 - 200 khz 27 lsb integral non-linearity (inl) (accuracy after calibration for offset and gain error) gain = 1x v ref = 4v, v cc = 5v adc clock = 50 - 200 khz 1.5 lsb gain = 20x v ref = 4v, v cc = 5v adc clock = 50 - 200 khz 2lsb gain error gain = 1x 2 % gain = 20x 2.5 % offset error gain = 1x v ref = 4v, v cc = 5v adc clock = 50 - 200 khz 4lsb gain = 20x v ref = 4v, v cc = 5v adc clock = 50 - 200 khz 6lsb clock frequency 50 200 khz conversion time 26 65 s avcc analog supply voltage v cc - 0.3 (1) v cc + 0.3 (2) v v ref reference voltage 2.0 avcc - 0.5 v v in input voltage gnd v cc v v diff input differential voltage 0 v ref /gain v adc conversion output 0 1023 lsb input bandwidth 4khz v int internal voltage reference 2.4 2.7 2.9 v r ref reference input resistance 32 k r ain analog input resistance 100 m 133 attiny26(l) 1477i?avr?10/06 attiny26 typical characteristics the following charts show typical behavior. these figures are not tested during manu- facturing. all current consumption measurements are performed with all i/o pins configured as inputs and with internal pull-ups enabled. a sine wave generator with rail- to-rail output is used as clock source. the power consumption in power-down mode is independent of clock selection. the current consumption is a function of several factors such as: operating voltage, operating frequency, loading of i/o pins, switching rate of i/o pins, code executed and ambient temperature. the dominating factors are operating voltage and frequency. the current drawn from capacitive loaded pins may be estimated (for one pin) as c l * v cc *f where c l = load capacitance, v cc = operating voltage and f = average switch- ing frequency of i/o pin. the parts are characterized at frequencies higher than test limits. parts are not guaran- teed to function properly at frequencies higher than the ordering code indicates. the difference between current consumption in power-down mode with watchdog timer enabled and power-down mode with watchdog timer disabled represents the dif- ferential current drawn by the watchdog timer. active supply current figure 71. active supply current vs. frequency (0.1 - 1.0 mhz) active supply current vs. frequency 0.1 - 1.0 mhz 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0. 9 1 frequency (mhz) i cc (ma) 5.5v 4.5v 4.0v 3.3v 2.7v 3.0v 5.0v 134 attiny26(l) 1477i?avr?10/06 figure 72. active supply current vs. frequency (1 - 20 mhz) figure 73. active supply current vs. v cc (internal rc oscillator, 8 mhz) active supply current vs. frequency 1 - 20 mhz 0 5 10 15 20 25 0 2 4 6 8 101214161820 frequency (mhz) i cc (ma) 5.5v 4.5v 4.0v 3.3v 2.7v 3.0v 5.0v active supply current vs. v cc internal rc oscillator, 8 mhz 0 2 4 6 8 10 12 14 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) i cc (ma) 85 c 25 c -40 c 135 attiny26(l) 1477i?avr?10/06 figure 74. active supply current vs. v cc (internal rc oscillator, 4 mhz) figure 75. active supply current vs. v cc (internal rc oscillator, 2 mhz) active supply current vs. v cc internal rc oscillator, 4 mhz 0 1 2 3 4 5 6 7 8 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) i cc (ma) 85 c 25 c -40 c active supply current vs. v cc internal rc oscillator, 2 mhz 0 0.5 1 1.5 2 2.5 3 3.5 4 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) i cc (ma) 85 c 25 c -40 c 136 attiny26(l) 1477i?avr?10/06 figure 76. active supply current vs. v cc (internal rc oscillator, 1 mhz) figure 77. active supply current vs. v cc (pll oscillator) active supply current vs. v cc internal rc oscillator, 1 mhz 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) i cc (ma) 85 c 25 c -40 c active supply current vs. v cc pll oscillator 0 5 10 15 20 25 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) i cc (ma) 85 c 25 c -40 c 137 attiny26(l) 1477i?avr?10/06 figure 78. active supply current vs. v cc (32 khz external oscillator) idle supply current figure 79. idle supply current vs. frequency (0.1 - 1.0 mhz) active supply current vs. v cc 32khz external oscillator 0 10 20 30 40 50 60 70 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) i cc (ua) 25 c idle supply current vs. frequency 0.1 - 1.0 mhz 0 0.1 0.2 0.3 0.4 0.5 0.6 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0. 9 1 frequency (mhz) i cc (ma) 5.5v 4.5v 4.0v 3.3v 2.7v 3.0v 5.0v 138 attiny26(l) 1477i?avr?10/06 figure 80. idle supply current vs. frequency (1 - 20 mhz) figure 81. idle supply current vs. v cc (internal rc oscillator, 8 mhz) idle supply current vs. frequency 1 - 20 mhz 0 2 4 6 8 10 12 02468101214161820 frequency (mhz) i cc (ma) 5.5v 4.5v 4.0v 3.3v 2.7v 3.0v 5.0v idle supply current vs. v cc internal rc oscillator, 8 mhz 0 1 2 3 4 5 6 7 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) i cc (ma) 85 c 25 c -40 c 139 attiny26(l) 1477i?avr?10/06 figure 82. idle supply current vs. v cc (internal rc oscillator, 4 mhz) figure 83. idle supply current vs. v cc (internal rc oscillator, 2 mhz) idle supply current vs. v cc internal rc oscillator, 4 mhz 0 0.5 1 1.5 2 2.5 3 3.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) i cc (ma) 85 c 25 c -40 c idle supply current vs. v cc internal rc oscillator, 2 mhz 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) i cc (ma) 85 c 25 c -40 c 140 attiny26(l) 1477i?avr?10/06 figure 84. idle supply current vs. v cc (internal rc oscillator, 1 mhz) figure 85. idle supply current vs. v cc (pll oscillator) idle supply current vs. v cc internal rc oscillator, 1 mhz 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) i cc (ma) 85 c 25 c -40 c idle supply current vs. v cc pll oscillator 0 2 4 6 8 10 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) i cc (ma) 85 c 25 c -40 c 141 attiny26(l) 1477i?avr?10/06 figure 86. idle supply current vs. v cc (32 khz external oscillator) power-down supply current figure 87. power-down supply current vs. v cc (watchdog timer disabled) idle supply current vs. v cc 32khz external oscillator 0 5 10 15 20 25 30 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) i cc (ua) 25 c power-down supply current vs. v cc watchdog timer disabled 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) i cc (ua) 85 c 25 c -40 c 142 attiny26(l) 1477i?avr?10/06 figure 88. power-down supply current vs. v cc (watchdog timer enabled) standby supply current figure 89. standby supply current vs. v cc (455 khz resonator, watchdog timer disabled) power-down supply current vs. v cc watchdog timer enabled 0 2 4 6 8 10 12 14 16 18 20 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) i cc (ua) 85 c 25 c -40 c standby supply current vs. v cc 455 khz resonator, watchdog timer disabled 0 10 20 30 40 50 60 70 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) i cc (ua) 143 attiny26(l) 1477i?avr?10/06 figure 90. standby supply current vs. v cc (1 mhz resonator, watchdog timer disabled) figure 91. standby supply current vs. v cc (2 mhz resonator, watchdog timer disabled) standby supply current vs. v cc 1 mhz resonator, watchdog timer disabled 0 10 20 30 40 50 60 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) i cc (ua) standby supply current vs. v cc 2 mhz resonator, watchdog timer disabled 0 10 20 30 40 50 60 70 80 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) i cc (ua) 144 attiny26(l) 1477i?avr?10/06 figure 92. standby supply current vs. v cc (2 mhz xtal, watchdog timer disabled) figure 93. standby supply current vs. v cc (4 mhz resonator, watchdog timer disabled) standby supply current vs. v cc 2 mhz xtal, watchdog timer disabled 0 10 20 30 40 50 60 70 80 9 0 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) i cc (ua) standby supply current vs. v cc 4 mhz resonator, watchdog timer disabled 0 20 40 60 80 100 120 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) i cc (ua) 145 attiny26(l) 1477i?avr?10/06 figure 94. standby supply current vs. v cc (4 mhz xtal, watchdog timer disabled) figure 95. standby supply current vs. v cc (6 mhz resonator, watchdog timer disabled) standby supply current vs. v cc 4 mhz xtal, watchdog timer disabled 0 20 40 60 80 100 120 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) i cc (ua) standby supply current vs. v cc 6 mhz resonator, watchdog timer disabled 0 20 40 60 80 100 120 140 160 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) i cc (ua) 146 attiny26(l) 1477i?avr?10/06 figure 96. standby supply current vs. v cc (6 mhz xtal, watchdog timer disabled) pin pull-up figure 97. i/o pin pull-up resistor current vs. input voltage (v cc = 5v) standby supply current vs. v cc 6 mhz xtal, watchdog timer disabled 0 20 40 60 80 100 120 140 160 180 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) i cc (ua) i/o pin pull-up resistor current vs. input voltage vcc = 5v 0 20 40 60 80 100 120 140 160 0123456 v op (v) i op (ua) 85 c 25 c -40 c 147 attiny26(l) 1477i?avr?10/06 figure 98. i/o pin pull-up resistor current vs. input voltage (v cc = 2.7v) figure 99. reset pull-up resistor curr ent vs. reset pin voltage (v cc = 5v) i/o pin pull-up resistor current vs. input voltage vcc = 2.7v 0 10 20 30 40 50 60 70 80 0 0.5 1 1.5 2 2.5 3 v op (v) i op (ua) 85 c 25 c -40 c reset pull-up resistor current vs. reset pin voltage vcc = 5v 0 20 40 60 80 100 120 v reset (v) i reset (ua) -40 c 25 c 85 c 148 attiny26(l) 1477i?avr?10/06 figure 100. reset pull-up resistor current vs. reset pin voltage (v cc = 2.7v) pin driver strength figure 101. i/o pin source current vs. output voltage (v cc = 5v) reset pull-up resistor current vs. reset pin voltage vcc = 2.7v 0 10 20 30 40 50 60 0 0.5 1 1.5 2 2.5 3 v reset (v) i reset (ua) -40 c 25 c 85 c i/o pin source current vs. output voltage vcc = 5v 0 10 20 30 40 50 60 70 80 9 0 01234 v oh (v) i oh (ma) 85 c 25 c -40 c 149 attiny26(l) 1477i?avr?10/06 figure 102. i/o pin source current vs. output voltage (v cc = 2.7v) figure 103. i/o pin sink current vs. output voltage (v cc = 5v) i/o pin source current vs. output voltage vcc = 2.7v 0 5 10 15 20 25 30 0 0.5 1 1.5 2 2.5 3 v oh (v) i oh (ma) 85 c 25 c -40 c i/o pin sink current vs. output voltage vcc = 5v 0 10 20 30 40 50 60 70 80 9 0 0 0.5 1 1.5 2 2.5 v ol (v) i ol (ma) 85 c 25 c -40 c 150 attiny26(l) 1477i?avr?10/06 figure 104. i/o pin sink current vs. output voltage (v cc = 2.7v) figure 105. reset pin as i/o ? source current vs. output voltage (v cc = 5v) i/o pin sink current vs. output voltage vcc = 2.7v 0 5 10 15 20 25 30 35 0 0.5 1 1.5 2 2.5 v ol (v) i ol (ma) 85 c 25 c -40 c reset pin as i/o - source current vs. output voltage vcc = 5v 0 0.2 0.4 0.6 0.8 1 1.2 1.4 0123 v oh (v) current (ma) 85 c 25 c -40 c 151 attiny26(l) 1477i?avr?10/06 figure 106. reset pin as i/o ? source current vs. output voltage (v cc = 2.7v) figure 107. reset pin as i/o ?sink current vs. output voltage (v cc = 5v) reset pin as i/o - source current vs. output voltage vcc = 2.7v 0 0.5 1 1.5 2 2.5 0 0.5 1 1.5 2 2.5 3 v oh (v) current (ma) 85 c 25 c -40 c reset pin as i/o - sink current vs. output voltage vcc = 5v 0 2 4 6 8 10 12 14 0 0.5 1 1.5 2 2.5 v ol (v) current (ma) 85 c 25 c -40 c 152 attiny26(l) 1477i?avr?10/06 figure 108. reset pin as i/o ? sink current vs. output voltage (v cc = 2.7v) pin thresholds and hysteresis figure 109. i/o pin input threshold voltage vs. v cc (v ih , i/o pin read as ?1?) reset pin as i/o - sink current vs. output voltage vcc = 2.7v 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 0 0.5 1 1.5 2 2.5 v ol (v) current (ma) 85 c 25 c -40 c i/o pin input threshold voltage vs. v cc vih, io pin read as '1' 0 0.5 1 1.5 2 2.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) threshold (v) 85 c 25 c -40 c 153 attiny26(l) 1477i?avr?10/06 figure 110. i/o pin input threshold voltage vs. v cc (v il , i/o pin read as ?0?) figure 111. i/o pin input hysteresis vs. v cc i/o pin input threshold voltage vs. v cc vil, io pin read as '0' 0 0.5 1 1.5 2 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) threshold (v) 85 c 25 c -40 c i/o pin input hysteresis vs. v cc 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 22.533.544.555.5 v cc (v) threshold (v) 85c 25c -40c 154 attiny26(l) 1477i?avr?10/06 figure 112. reset pin as i/o ? input threshold voltage vs. v cc (v ih , reset pin read as ?1?) figure 113. reset pin as i/o ? input threshold voltage vs. v cc (v il , reset pin read as ?0?) reset pin as i/o - input threshold voltage vs. v cc vih, reset pin read as '1' 0 0.5 1 1.5 2 2.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) threshold (v) 85 c 25 c -40 c reset pin as i/o - input threshold voltage vs. v cc vil, reset pin read as '0' 0 0.5 1 1.5 2 2.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) threshold (v) 85 c 25 c -40 c 155 attiny26(l) 1477i?avr?10/06 figure 114. reset pin as i/o ? pin hysteresis vs. v cc figure 115. reset input thresh old voltage vs. v cc (v ih , reset pin read as ?1?) reset pin as i/o - pin hysteresis vs. v cc 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 22.533.544.555.5 v cc (v) threshold (v) 85c 25c -40c reset input threshold voltage vs. v cc vih, reset pin read as '1' 0 0.5 1 1.5 2 2.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) threshold (v) 85 c 25 c -40 c 156 attiny26(l) 1477i?avr?10/06 figure 116. reset input thresh old voltage vs. v cc (v il , reset pin read as ?0?) figure 117. reset input pin hysteresis vs. v cc reset input threshold voltage vs. v cc vil, reset pin read as '0' 0 0.5 1 1.5 2 2.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) threshold (v) 85 c 25 c -40 c reset input pin hysteresis vs. v cc 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) threshold (v) 85 c 25 c -40 c 157 attiny26(l) 1477i?avr?10/06 bod thresholds and analog comparator offset figure 118. bod thresholds vs. temperature (bod level is 4.0v) figure 119. bod thresholds vs. temperature (bod level is 2.7v) bod thresholds vs. temperature bodlevel is 4.0v 3.8 3. 9 4 4.1 4.2 4.3 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 9 0 100 temperature (c) threshold (v) rising v cc falling v cc bod thresholds vs. temperature bodlevel is 2.7v 2.6 2.7 2.8 2. 9 3 3.1 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 9 0 100 temperature (c) threshold (v) rising v cc falling v cc 158 attiny26(l) 1477i?avr?10/06 figure 120. bandgap voltage vs. v cc figure 121. analog comparator offset voltage vs. common mode voltage (v cc = 5.0v) bandgap vs. v cc 1.216 1.218 1.22 1.222 1.224 1.226 1.228 1.23 1.232 1.234 1.236 2.5 3 3.5 4 4.5 5 5.5 vcc (v) bandgap voltage (v) 85 c 25 c -40 c analog comparator offset voltage vs. common mode voltage vcc = 5v 0 0.001 0.002 0.003 0.004 0.005 0.006 0.007 0.008 0.00 9 01234 common mode voltage (v) comparator offset voltage (v) 85c 25c -40c 159 attiny26(l) 1477i?avr?10/06 figure 122. analog comparator offset voltage vs. common mode voltage (v cc = 2.7v) internal oscillator speed figure 123. watchdog oscillator frequency vs. v cc analog comparator offset voltage vs. common mode voltage vcc = 2.7v 0 0.001 0.002 0.003 0.004 0.005 0.006 0.007 0.008 0.00 9 0 0.5 1 1.5 2 2.5 3 common mode voltage (v) comparator offset voltage (v) 85c 25c -40c watchdog oscillator frequency vs. v cc 1.05 1.1 1.15 1.2 1.25 1.3 1.35 1.4 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) f rc (mhz) 85 c 25 c -40 c 160 attiny26(l) 1477i?avr?10/06 figure 124. calibrated 8 mhz rc oscillator frequen cy vs. temperature figure 125. calibrated 8 mhz rc osc illator frequency vs. v cc calibrated 8mhz rc oscillator frequency vs. temperature 6.4 6. 9 7.4 7. 9 8.4 8. 9 -60 -40 -20 0 20 40 60 80 100 t a (?c) f rc (mhz) 5.0v 3.5v 2.7v calibrated 8mhz rc oscillator frequency vs. v cc 6 6.5 7 7.5 8 8.5 9 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) f rc (mhz) 85 c 25 c -40 c 161 attiny26(l) 1477i?avr?10/06 figure 126. calibrated 8 mhz rc oscillator frequen cy vs. osccal value figure 127. calibrated 4 mhz rc oscillator frequen cy vs. temperature calibrated 8mhz rc oscillator frequency vs. osccal value 3.5 5.5 7.5 9 .5 11.5 13.5 15.5 17.5 0 1632486480 9 6 112 128 144 160 176 1 9 2 208 224 240 osccal value f rc (mhz) calibrated 4mhz rc oscillator frequency vs. temperature 3.4 3.5 3.6 3.7 3.8 3. 9 4 4.1 4.2 4.3 -60 -40 -20 0 20 40 60 80 100 t a (?c) f rc (mhz) 5.0v 3.5v 2.7v 162 attiny26(l) 1477i?avr?10/06 figure 128. calibrated 4 mhz rc osc illator frequency vs. v cc figure 129. calibrated 4 mhz rc oscillator frequen cy vs. osccal value calibrated 4mhz rc oscillator frequency vs. v cc 3.4 3.5 3.6 3.7 3.8 3. 9 4 4.1 4.2 4.3 4.4 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) f rc (mhz) 85 c 25 c -40 c calibrated 4mhz rc oscillator frequency vs. osccal value 1.6 2.6 3.6 4.6 5.6 6.6 7.6 8.6 9 .6 0 1632486480 9 6 112 128 144 160 176 1 9 2 208 224 240 osccal value f rc (mhz) 163 attiny26(l) 1477i?avr?10/06 figure 130. calibrated 2 mhz rc oscillator frequen cy vs. temperature figure 131. calibrated 2 mhz rc osc illator frequency vs. v cc calibrated 2mhz rc oscillator frequency vs. temperature 1.75 1.8 1.85 1. 9 1. 9 5 2 2.05 2.1 2.15 -60 -40 -20 0 20 40 60 80 100 t a (?c) f rc (mhz) 5.0v 3.5v 2.7v calibrated 2mhz rc oscillator frequency vs. v cc 1.7 1.75 1.8 1.85 1. 9 1. 9 5 2 2.05 2.1 2.15 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) f rc (mhz) 85 c 25 c -40 c 164 attiny26(l) 1477i?avr?10/06 figure 132. calibrated 2 mhz rc oscillator frequen cy vs. osccal value figure 133. calibrated 1 mhz rc oscillator frequen cy vs. temperature calibrated 2mhz rc oscillator frequency vs. osccal value 0.8 1.3 1.8 2.3 2.8 3.3 3.8 4.3 0 1632486480 9 6 112 128 144 160 176 1 9 2 208 224 240 osccal value f rc (mhz) calibrated 1 mhz rc oscillator frequency vs. temperature 0. 9 0. 9 2 0. 9 4 0. 9 6 0. 9 8 1 1.02 1.04 -60 -40 -20 0 20 40 60 80 100 v cc (v) f rc (mhz) 5.0 v 3.5 v 2.7 v 165 attiny26(l) 1477i?avr?10/06 figure 134. calibrated 1 mhz rc osc illator frequency vs. v cc figure 135. calibrated 1 mhz rc oscillator frequen cy vs. osccal value calibrated 1mhz rc oscillator frequency vs. v cc 0.85 0. 9 0. 9 5 1 1.05 1.1 22.533.544.555.5 v cc (v) f rc (mhz) 85c 25c -40 c calibrated 1mhz rc oscillator frequency vs. osccal value 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 0 1632486480 9 6 112 128 144 160 176 1 9 2 208 224 240 osccal value f rc (mhz) 166 attiny26(l) 1477i?avr?10/06 current consumption of peripheral units figure 136. brown-out detector current vs. v cc figure 137. adc current vs. v cc (aref = av cc ) brownout detector current vs. v cc 0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) i cc (ma) 25 c 85 c -40 c adc current vs. v cc aref = avcc 0 50 100 150 200 250 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) i cc (ua) 85 c 25 c -40 c 167 attiny26(l) 1477i?avr?10/06 figure 138. aref external reference current vs. v cc figure 139. analog comparator current vs. v cc aref external reference current vs. vcc 0 50 100 150 200 250 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) i cc (ua) 85 c 25 c -40 c analog comparator current vs. v cc 0 20 40 60 80 100 120 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) i cc (ua) 85 c 25 c -40 c 168 attiny26(l) 1477i?avr?10/06 figure 140. programming current vs. v cc current consumption in reset and reset pulsewidth figure 141. reset supply current vs. v cc (0.1 - 1.0 mhz, excluding current through the reset pull-up) programming current vs. vcc 0 1 2 3 4 5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) i cc (ma) 85 c 25 c -40 c reset supply current vs. v cc 0.1 - 1.0 mhz, excluding current through the reset pullup 0 0.5 1 1.5 2 2.5 3 3.5 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0. 9 1 frequency (mhz) i cc (ma) 5.5v 4.5v 4.0v 3.3v 2.7v 3.0v 5.0v 169 attiny26(l) 1477i?avr?10/06 figure 142. reset supply current vs. v cc (1 - 20 mhz, excluding current through the reset pull-up) figure 143. reset pulsewidth vs. v cc reset supply current vs. v cc 1 - 20 mhz, excluding current through the reset pullup 0 2 4 6 8 10 12 14 16 18 20 02468101214161820 frequency (mhz) i cc (ma) 5.5v 4.5v 4.0v 3.3v 2.7v 3.0v 5.0v reset pulse width vs. v cc 0 200 400 600 800 1000 1200 0123 v cc (v) pulsewidth (ns) 85 c 25 c -40 c 170 attiny26(l) 1477i?avr?10/06 register summary address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page $3f ($5f) sreg i t h s v n z c 11 $3e ($5e) reserved $3d ($5d) sp sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 12 $3c ($5c) reserved $3b ($5b) gimsk - int0 pcie1 pcie0 - - - -60 $3a ($5a) gifr - intf0 pcif - - - - -61 $39 ($59) timsk - ocie1a ocie1b - - toie1 toie0 -61 $38 ($58) tifr -ocf1aocf1b - - tov1 tov0 -62 $37 ($57) reserved $36 ($56) reserved $35 ($55) mcucr -pudsesm1sm0 -isc01isc00 38 $34 ($54) mcusr - - - - wdrf borf extrf porf 37 $33 ($53) tccr0 - - - - psr0 cs02 cs01 cs00 68 $32 ($52) tcnt0 timer/counter0 (8-bit) 69 $31 ($51) osccal oscillator calibration register 30 $30 ($50) tccr1a com1a1 com1a0 com1b1 com1b0 foc1a foc1b pwm1a pwm1b 72 $2f ($4f) tccr1b ctc1 psr1 - - cs13 cs12 cs11 cs10 73 $2e ($4e) tcnt1 timer/counter1 (8-bit) 74 $2d ($4d) ocr1a timer/counter1 output compare register a (8-bit) 74 $2c ($4c) ocr1b timer/counter1 output compare register b (8-bit) 75 $2b ($4b) ocr1c timer/counter1 output compare register c (8-bit) 75 $2a ($4a) reserved $29 ($49) pllcsr - - - - - pcke plle plock $28 ($48) reserved $27 ($47) reserved $26 ($46) reserved $25 ($45) reserved $24 ($44) reserved $23 ($43) reserved $22 ($42) reserved $21 ($41) wdtcr - - - wdce wde wdp2 wdp1 wdp0 80 $20 ($40) reserved $1f ($3f) reserved $1e ($3e) eear - eear6 eear5 eear4 eear3 eear2 eear1 eear0 19 $1d ($3d) eedr eeprom data register (8-bit) 20 $1c ($3c) eecr - - - - eerie eemwe eewe eere 20 $1b ($3b) porta porta7 porta6 porta5 porta4 porta3 porta2 porta1 porta0 $1a ($3a) ddra dda7 dda6 dda 5 dda4 dda3 dda2 dda1 dda0 $19 ($39) pina pina7 pina6 pina5 pina4 pina3 pina2 pina1 pina0 $18 ($38) portb portb7 portb6 portb5 p ortb4 portb3 portb2 portb1 portb0 $17 ($37) ddrb ddb7 ddb6 ddb 5 ddb4 ddb3 ddb2 ddb1 ddb0 $16 ($36) pinb pinb7 pinb6 pinb5 pinb4 pinb3 pinb2 pinb1 pinb0 $15 ($35) reserved $14 ($34) reserved $13 ($33) reserved $12 ($32) reserved $11 ($31) reserved $10 ($30) reserved $0f ($2f) usidr universal serial in terface data register (8-bit) 83 $0e ($2e) usisr usisif usioif usipf usi dc usicnt3 usicnt2 usicnt1 usicnt0 83 $0d ($2d) usicr usisie usioie usiwm1 usiwm0 usics1 usics0 usiclk usitc 84 $0c ($2c) reserved $0b ($2)b reserved $0a ($2a) reserved $09 ($29) reserved $08 ($28) acsr acd acbg aco aci acie acme acis1 acis0 93 $07 ($27) admux refs1 refs0 adlar mux4 mux3 mux2 mux1 mux0 103 $06 ($26) adcsr aden adsc adfr a dif adie adps2 adps1 adps0 105 $05 ($25) adch adc data register high byte 106 $04 ($24) adcl adc data register low byte 106 ? reserved $00 ($20) reserved 171 attiny26(l) 1477i?avr?10/06 instruction set summary mnemonic operands description operation flags # clocks arithmetic and logic instructions add rd, rr add two registers rd rd + rr z,c,n,v,h 1 adc rd, rr add with carry two registers rd rd + rr + c z,c,n,v,h 1 adiw rdl, k add immediate to word rdh:rdl rdh:rdl + k z,c,n,v,s 2 sub rd, rr subtract two registers rd rd - rr z,c,n,v,h 1 subi rd, k subtract constant from register rd rd - k z,c,n,v,h 1 sbc rd, rr subtract with carry two registers rd rd - rr - c z,c,n,v,h 1 sbci rd, k subtract with carry constant from reg. rd rd - k - c z,c,n,v,h 1 sbiw rdl, k subtract immediate from word rdh:rdl rdh:rdl - k z,c,n,v,s 2 and rd, rr logical and registers rd rd ? rr z,n,v 1 andi rd, k logical and register and constant rd rd ? k z,n,v 1 or rd, rr logical or registers rd rd v rr z,n,v 1 ori rd, k logical or register and constant rd rd v k z,n,v 1 eor rd, rr exclusive or registers rd rd rr z,n,v 1 com rd one?s complement rd $ff - rd z,c,n,v 1 neg rd two?s complement rd $00 - rd z,c,n,v,h 1 sbr rd, k set bit(s) in register rd rd v k z,n,v 1 cbr rd, k clear bit(s) in register rd rd ? ($ff - k) z,n,v 1 inc rd increment rd rd + 1 z,n,v 1 dec rd decrement rd rd - 1 z,n,v 1 tst rd test for zero or minus rd rd ? rd z,n,v 1 clr rd clear register rd rd rd z,n,v 1 ser rd set register rd $ff none 1 branch instructions rjmp k relative jump pc pc + k + 1 none 2 ijmp indirect jump to (z) pc z none 2 rcall k relative subroutine call pc pc + k + 1 none 3 icall indirect call to (z) pc znone3 ret subroutine return pc stack none 4 reti interrupt return pc stack i 4 cpse rd, rr compare, skip if equal if (rd = rr) pc pc + 2 or 3 none 1/2/3 cp rd, rr compare rd - rr z,n,v,c,h 1 cpc rd, rr compare with carry rd - rr - c z,n,v,c,h 1 cpi rd, k compare register with immediate rd - k z,n,v,c,h 1 sbrc rr, b skip if bit in register cleared if (rr(b) = 0) pc pc + 2 or 3 none 1/2/3 sbrs rr, b skip if bit in register is set if (rr(b) = 1) pc pc + 2 or 3 none 1/2/3 sbic p, b skip if bit in i/o register cleared if (p(b) = 0) pc pc + 2 or 3 none 1/2/3 sbis p, b skip if bit in i/o register is set if (p(b) = 1) pc pc + 2 or 3 none 1/2/3 brbs s, k branch if status flag set if (sreg(s) = 1) then pc pc + k + 1 none 1/2 brbc s, k branch if status flag cleared if (sreg(s) = 0) then pc pc + k + 1 none 1/2 breq k branch if equal if (z = 1) then pc pc + k + 1 none 1/2 brne k branch if not equal if (z = 0) then pc pc + k + 1 none 1/2 brcs k branch if carry set if (c = 1) then pc pc + k + 1 none 1/2 brcc k branch if carry cleared if (c = 0) then pc pc + k + 1 none 1/2 brsh k branch if same or higher if (c = 0) then pc pc + k + 1 none 1/2 brlo k branch if lower if (c = 1) then pc pc + k + 1 none 1/2 brmi k branch if minus if (n = 1) then pc pc + k + 1 none 1/2 brpl k branch if plus if (n = 0) then pc pc + k + 1 none 1/2 brge k branch if greater or equal, signed if (n v = 0) then pc pc + k + 1 none 1/2 brlt k branch if less than zero, signed if (n v = 1) then pc pc + k + 1 none 1/2 brhs k branch if half-carry flag set if (h = 1) then pc pc + k + 1 none 1/2 brhc k branch if half-carry flag cleared if (h = 0) then pc pc + k + 1 none 1/2 brts k branch if t-flag set if (t = 1) then pc pc + k + 1 none 1/2 brtc k branch if t-flag cleared if (t = 0) then pc pc + k + 1 none 1/2 brvs k branch if overflow flag is set if (v = 1) then pc pc + k + 1 none 1/2 brvc k branch if overflow flag is cleared if (v = 0) then pc pc + k + 1 none 1/2 brie k branch if interrupt enabled if (i = 1) then pc pc + k + 1 none 1/2 brid k branch if interrupt disabled if (i = 0) then pc pc + k + 1 none 1/2 data transfer instructions mov rd, rr move between registers rd rr none 1 ldi rd, k load immediate rd knone1 ld rd, x load indirect rd (x) none 2 ld rd, x+ load indirect and post-inc. rd (x), x x + 1 none 2 ld rd, -x load indirect and pre-dec. x x - 1, rd (x) none 2 172 attiny26(l) 1477i?avr?10/06 ld rd, y load indirect rd (y) none 2 ld rd, y+ load indirect and post-inc. rd (y), y y + 1 none 2 ld rd, -y load indirect and pre-dec. y y - 1, rd (y) none 2 ldd rd,y+q load indirect with displacement rd (y + q) none 2 ld rd, z load indirect rd (z) none 2 ld rd, z+ load indirect and post-inc. rd (z), z z + 1 none 2 ld rd, -z load indirect and pre-dec. z z - 1, rd (z) none 2 ldd rd, z+q load indirect with displacement rd (z + q) none 2 lds rd, k load direct from sram rd (k) none 2 st x, rr store indirect (x) rr none 2 st x+, rr store indirect and post-inc. (x) rr, x x + 1 none 2 st -x, rr store indirect and pre-dec. x x - 1, (x) rr none 2 st y, rr store indirect (y) rr none 2 st y+, rr store indirect and post-inc. (y) rr, y y + 1 none 2 st -y, rr store indirect and pre-dec. y y - 1, (y) rr none 2 std y+q, rr store indirect with displacement (y + q) rr none 2 st z, rr store indirect (z) rr none 2 st z+, rr store indirect and post-inc. (z) rr, z z + 1 none 2 st -z, rr store indirect and pre-dec. z z - 1, (z) rr none 2 std z+q, rr store indirect with displacement (z + q) rr none 2 sts k, rr store direct to sram (k) rr none 2 lpm load program memory r0 (z) none 3 lpm rd, z load program memory rd (z) none 3 in rd, p in port rd pnone1 out p, rr out port p rr none 1 push rr push register on stack stack rr none 2 pop rd pop register from stack rd stack none 2 bit and bit-test instructions sbi p, b set bit in i/o register i/o(p,b) 1none2 cbi p, b clear bit in i/o register i/o(p,b) 0none2 lsl rd logical shift left rd(n+1) rd(n), rd(0) 0 z,c,n,v 1 lsr rd logical shift right rd(n) rd(n+1), rd(7) 0 z,c,n,v 1 rol rd rotate left through carry rd(0) c, rd(n+1) rd(n), c rd(7) z,c,n,v 1 ror rd rotate right through carry rd(7) c, rd(n) rd(n+1), c rd(0) z,c,n,v 1 asr rd arithmetic shift right rd(n) rd(n+1), n = 0..6 z,c,n,v 1 swap rd swap nibbles rd(3..0) rd(7..4), rd(7..4) rd(3..0) none 1 bset s flag set sreg(s) 1 sreg(s) 1 bclr s flag clear sreg(s) 0 sreg(s) 1 bst rr, b bit store from register to t t rr(b) t 1 bld rd, b bit load from t to register rd(b) tnone1 sec set carry c 1c1 clc clear carry c 0c1 sen set negative flag n 1n1 cln clear negative flag n 0n1 sez set zero flag z 1z1 clz clear ze ro flag z 0z1 sei global interrupt enable i 1i1 cli global interrupt disable i 0i1 ses set signed test flag s 1s1 cls clear signed test flag s 0s1 sev set two?s complement overflow v 1v1 clv clear two?s complement overflow v 0v1 set set t in sreg t 1t1 clt clear t in sreg t 0t1 seh set half-carry flag in sreg h 1h1 clh clear half-carry flag in sreg h 0h1 nop no operation none 1 sleep sleep (see specific descr. for sleep function) none 1 wdr watchdog reset (see specific descr. for wdr/timer) none 1 instruction set summary (continued) mnemonic operands description operation flags # clocks 173 attiny26(l) 1477i?avr?10/06 notes: 1. this device can also be supplied in wafer form. please contact your local atmel sales office for detailed ordering info rmation and minimum quantities. 2. pb-free packaging alternative, complies to the european dire ctive for restriction of hazardous substances (rohs direc- tive). also halide free and fully green. ordering information speed (mhz) power supply ordering code package (1) operational range 8 2.7 - 5.5v attiny26l-8pc attiny26l-8sc attiny26l-8mc 20p3 20s 32m1-a commercial (0 c to 70 c) attiny26l-8pi attiny26l-8si attiny26l-8mi attiny26l-8pu (2) attiny26l-8su (2) ATTINY26L-8MU (2) 20p3 20s 32m1-a 20p3 20s 32m1-a industrial (-40 c to 85 c) 16 4.5 - 5.5v attiny26-16pc attiny26-16sc attiny26-16mc 20p3 20s 32m1-a commercial (0 c to 70 c) attiny26-16pi attiny26-16si attiny26-16mi attiny26-16pu (2) attiny26-16su (2) attiny26-16mu (2) 20p3 20s 32m1-a 20p3 20s 32m1-a industrial (-40 c to 85 c) package type 20p3 20-lead, 0.300" wide, plastic dual inline package (pdip) 20s 20-lead, 0.300" wide, plastic gull wing small outline (soic) 32m1-a 32-pad, 5 x 5 x 1.0 body, lead pitch 0.50 mm quad flat no-lead/micro lead frame package (qfn/mlf) 174 attiny26(l) 1477i?avr?10/06 packaging information 20p3 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 20p3 , 20-lead (0.300"/7.62 mm wide) plastic dual inline package (pdip) c 20p3 1/12/04 pin 1 e1 a1 b e b1 c l seating plane a d e eb ec common dimensions (unit of measure = mm) symbol min nom max note a ? ? 5.334 a1 0.381 ? ? d 25.493 ? 25.984 note 2 e 7.620 ? 8.255 e1 6.096 ? 7.112 note 2 b 0.356 ? 0.559 b1 1.270 ? 1.551 l 2.921 ? 3.810 c 0.203 ? 0.356 eb ? ? 10.922 ec 0.000 ? 1.524 e 2.540 typ notes: 1. this package conforms to jedec reference ms-001, variation ad. 2. dimensions d and e1 do not include mold flash or protrusion. mold flash or protrusion shall not exceed 0.25 mm (0.010"). 175 attiny26(l) 1477i?avr?10/06 20s 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 20s2 , 20-lead, 0.300" wide body, plastic gull wing small outline package (soic) 1/9/02 20s2 a l a1 end view side view top view h e b n 1 e a d c common dimensions (unit of measure = inches) symbol min nom max note notes: 1. this drawing is for general information only; refer to jedec drawing ms-013, variation ac for additional information. 2. dimension "d" does not include mold flash, protrusions or gate burrs. mold flash, protrusions and gate burrs shall not exc eed 0.15 mm (0.006") per side. 3. dimension "e" does not include inter-lead flash or protrusion. inter-lead flash and protrusions shall not exceed 0.25 mm (0.010") per side. 4. "l" is the length of the terminal for soldering to a substrate. 5. the lead width "b", as measured 0.36 mm (0.014") or greater above the seating plane, shall not exceed a maximum value of 0.61 mm (0.024") per side. a 0.0926 0.1043 a1 0.0040 0.0118 b 0.0130 0.0200 4 c 0.0091 0.0125 d 0.4961 0.5118 1 e 0.2914 0.2992 2 h 0.3940 0.4190 l 0.0160 0.050 3 e 0.050 bsc 176 attiny26(l) 1477i?avr?10/06 32m1-a 2 3 25 orch a rd p a rkw a y sa n jo s e, ca 951 3 1 title drawing no. r rev. 3 2m1-a , 3 2-p a d, 5 x 5 x 1.0 mm body, le a d pitch 0.50 mm, e 3 2m1-a 5/25/06 3 .10 mm expo s ed p a d, micro le a d fr a me p a ck a ge (mlf) common dimen s ion s (unit of me asu re = mm) s ymbol min nom max note d1 d e1 e e b a 3 a2 a1 a d2 e2 0.0 8 c l 1 2 3 p p 0 1 2 3 a 0. 8 0 0.90 1.00 a1 ? 0.02 0.05 a2 ? 0.65 1.00 a 3 0.20 ref b 0.1 8 0.2 3 0. 3 0 d d1 d2 2.95 3 .10 3 .25 4.90 5.00 5.10 4.70 4.75 4. 8 0 4.70 4.75 4. 8 0 4.90 5.00 5.10 e e1 e2 2.95 3 .10 3 .25 e 0.50 b s c l 0. 3 0 0.40 0.50 p ? ? 0.60 ? ? 12 o note: jedec s t a nd a rd mo-220, fig. 2 (anvil s ing u l a tion), vhhd-2. top view s ide view bottom view 0 pin 1 id pin #1 notch (0.20 r) k 0.20 ? ? k k 177 attiny26(l) 1477i?avr?10/06 errata the revision letter refers to the revision of the device. attiny26 rev. b/c/d ? first analog comparator conversion may be delayed 1. first analog comparator conversion may be delayed if the device is powered by a slow rising vcc, the first analog comparator conver- sion will take longer than ex pected on some devices. problem fix/workaround when the device has been powered or reset, disable then enable the analog com- parator before the first conversion. 178 attiny26(l) 1477i?avr?10/06 datasheet revision history please note that the referring page numbers in this section are referred to this docu- ment. the referring revision in this section are referring to the document revision. rev. 1477i-10/06 1. updated ?errata? on page 177 rev. 1477h-04/06 1. updated typos. 2. added ?resources? on page 6. 3. updated features in ?system control and reset? on page 33. 4. updated ?prescaling and conv ersion timing? on page 98. 5. updated algorithm for ?enter programming mode? on page 114. rev. 1477g-03/05 1. mlf-package alternative changed to ?quad flat no-lead/micro lead frame package qfn/mlf?. 2. updated ?electrical characteristics? on page 128 3. updated ?ordering information? on page 173 rev. 1477f-12/04 1. updated table 16 on page 34, table 9 on page 29, and table 29 on page 59. 2. added table 20 on page 41. 3. added ?changing channel or reference selection? on page 100. 4. updated ?offset compensation schemes? on page 107. 5. updated ?electrical characteristics? on page 128. 6. updated package information for ?20p3? on page 174. 7. rearranged some sections in the datasheet. rev. 1477e-10/03 1. removed preliminary references. 2. updated ?features? on page 1. 3. removed ssop package reference from ?pin configuration? on page 2. 4. updated v rst and t rst in table 16 on page 34. 5. updated ?calibrated internal rc oscillator? on page 30. 6. updated dc characteristics for v ol , i il , i ih , i cc power down and v acio in ?elec- trical characteristics? on page 128. 7. updated v int , inl and gain error in ?adc characteristics? on page 131 and page 132. fixed typo in ?absolute accuracy? on page 132. 179 attiny26(l) 1477i?avr?10/06 8. added figure 106 in ?pin driver strengt h? on page 148, figure 120, figure 121 and figure 122 in ?bod thresholds and analog comparator offset? on page 157. updated figure 117 and figure 118. 9. removed lpm rd, z+ from ?instruction set summary? on page 171. this instruction is not supported in attiny26. rev. 1477d-05/03 1. updated ?packaging information? on page 174. 2. removed adhsm from ?adc characteristics? on page 131. 3. added section ?eeprom write during power-down sleep mode? on page 21. 4. added section ?default clock source? on page 27. 5. corrected pll lock value in the ?bit 0 ? plock: pll lock detector? on page 76. 6. added information about conversion time when selecting differential chan- nels on page 99. 7. corrected {ddxn, portxn} value on page 45. 8. added section ?unconnected pins? on page 48. 9. added note for rstdisbl fuse in table 50 on page 110. 10. corrected data value in figure 61 on page 118. 11. added wd_fuse period in table 60 on page 125. 12. updated ?adc characteristics? on page 131 and added table 66, ?adc char- acteristics, differential channels, ta = -40c to 85c,? on page 132. 13. updated ?attiny26 typical characteristics? on page 133. 14. added lpm rd, z and lpm rd, z+ in ?instruction set summary? on page 171. rev. 1477c-09/02 1. changed the endurance on the flash to 10,000 write/erase cycles. rev. 1477b-04/02 1. removed all references to power save sleep mode in the section ?system clock and clock options? on page 24. 2. updated the section ?analog to digi tal converter? on page 96 with more details on how to read the conversion result for both differential and single- ended conversion. 3. updated ?ordering information? on page 173 and added qfn/mlf package information. rev. 1477a-03/02 1. initial version. 180 attiny26(l) 1477i?avr?10/06 i attiny26(l) 1477i?avr?10/06 table of contents features............... .............. .............. ............... .............. .............. .......... 1 pin configuration....... ................. ................ ................. .............. .......... 2 description .......... .............. .............. ............... .............. .............. .......... 3 block diagram ...................................................................................................... 4 pin descriptions.................................................................................................... 5 resources ........... .............. .............. ............... .............. .............. .......... 6 about code examples........... ................ ................. ................ ............. 7 avr cpu core ........... ................. ................ ................. .............. .......... 8 architectural overview.......................................................................................... 8 general purpose register file ............................................................................. 9 alu ? arithmetic logic unit................................................................................ 10 status register ? sreg ..................................................................................... 11 stack pointer ? sp.............................................................................................. 12 program and data addressing modes................................................................ 12 memories ........... .............. .............. .............. .............. .............. ........... 17 in-system programmable flash program memory ............................................ 18 sram data memory........................................................................................... 18 eeprom data memory............ ................ ................ ................ ................ .......... 19 i/o memory ......................................................................................................... 22 system clock and clock options ............. .............. .............. ........... 24 clock systems and their distribution .................................................................. 24 clock sources..................................................................................................... 26 default clock source .......................................................................................... 27 crystal oscillator................................................................................................. 27 low-frequency crystal oscillator ........................................................................ 28 external rc oscillator ........................................................................................ 29 calibrated internal rc oscillator .............. .......................................................... 30 external clock..................................................................................................... 31 high frequency pll clock ? pllclk................................................................ 32 system control and reset ..... ............... ................. ................ ........... 33 power-on reset .................................................................................................. 34 external reset .................................................................................................... 35 brown-out detection ........................................................................................... 36 watchdog reset ................................................................................................. 36 mcu status register ? mcusr......................................................................... 37 power management and sleep modes......... .............. .............. ........ 38 mcu control register ? mcucr ....................................................................... 38 ii attiny26(l) 1477i?avr?10/06 idle mode ............................................................................................................ 39 adc noise reduction mode............................................................................... 39 power-down mode.............................................................................................. 39 standby mode..................................................................................................... 40 minimizing power consumption ......................................................................... 41 i/o ports............. .............. .............. .............. .............. .............. ........... 43 introduction ......................................................................................................... 43 ports as general digital i/o ................................................................................ 44 alternate port functions ..................................................................................... 48 register description for i/o ports ....................................................................... 58 interrupts ................ ................ ................ ................. ................ ........... 59 interrupt vectors ................................................................................................. 59 interrupt handling ............................................................................................... 60 external interrupt............ .............. .............. .............. .............. ........... 64 pin change interrupt........................................................................................... 64 timer/counters ........ ................ ................. ................ .............. ........... 66 timer/counter0 prescaler................................................................................... 66 timer/counter1 prescaler................................................................................... 67 8-bit timer/counter0........................................................................................... 67 8-bit timer/counter1........................................................................................... 69 watchdog timer............ ................ .............. .............. .............. ........... 80 universal serial interface ? usi.......... ................. ................ ............. 82 overview............................................................................................................. 82 register descriptions.......................................................................................... 83 functional descriptions ...................................................................................... 87 alternative usi usage ........................................................................................ 92 analog comparator ............. ................ ................. ................ ............. 93 analog to digital converter . ............... ................. ................ ............. 96 features.............................................................................................................. 96 operation ............................................................................................................ 97 prescaling and conversion timing ..................................................................... 98 changing channel or reference selection ...................................................... 100 adc noise canceler function.......................................................................... 101 adc conversion result.................................................................................... 101 scanning multiple channels ............................................................................. 107 adc noise canceling techniques ................................................................... 107 offset compensation schemes ........................................................................ 107 iii attiny26(l) 1477i?avr?10/06 memory programming........... ................ ................. ................ ......... 109 program and data memory lock bits............................................................... 109 fuse bits........................................................................................................... 110 signature bytes ................................................................................................ 111 calibration byte ................................................................................................ 111 page size ......................................................................................................... 111 parallel programming parameters, pin mapping, and commands .................. 111 parallel programming ....................................................................................... 114 serial downloading........................................................................................... 123 serial programming pin mapping ..................................................................... 123 electrical characteristics...... ................ ................. ................ ......... 128 absolute maximum ratings*............................................................................. 128 dc characteristics............................................................................................ 128 external clock drive waveforms ...................................................................... 130 external clock drive ......................................................................................... 130 adc characteristics ......................................................................................... 131 attiny26 typical characteristics .............. .............. .............. ......... 133 register summary ..... ................. ................ .............. .............. ......... 170 instruction set summary ...... ................ ................. ................ ......... 171 ordering information........... ................ ................. ................ ........... 173 packaging information .......... ................ ................. ................ ......... 174 20p3 ................................................................................................................. 174 20s ................................................................................................................... 175 32m1-a ............................................................................................................. 176 errata ............... ................ .............. .............. .............. .............. ......... 177 attiny26, all revisions....................................................................................... 177 datasheet revision history ... ............... ................. ................ ......... 178 changes from rev. 1477g-03/05 to rev. 1477h-04/06................................... 178 changes from rev. 1477f-12/04 to rev. 1477g-03/05 ................................... 178 changes from rev. 1477e-10/03 to rev. 1477f-12/04 ................................... 178 changes from rev. 1477d-05/03 to rev. 1477e-10/03 ................................... 178 changes from rev. 1477c-09/02 to rev. 1477d-05/03................................... 179 changes from rev. 1477b-04/02 to rev. 1477c-09/02 ................................... 179 changes from rev. 1477a-03/02 to rev. 1477b-04/02 ................................... 179 table of contents ................ .............. .............. .............. .............. ......... i iv attiny26(l) 1477i?avr?10/06 1477i?avr?10/06 disclaimer: the information in this document is provided in connection with atmel products. no license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of atmel products. except as set forth in atmel?s terms and condi- tions of sale located on atmel? s web site, atmel assumes no liability whatsoever and disclaims any express, implied or statutor y warranty relating to its products including, but not limited to , the implied warranty of merchantability, fitness for a particu lar purpose, or non-infringement. in no event shall atmel be liable for any direct, indirect, conseque ntial, punitive, special or i nciden- tal damages (including, without limitation, damages for loss of profits, business interruption, or loss of information) arising out of the use or inability to use this document, even if at mel has been advised of the possibility of such damages. atmel makes no representations or warranties with respect to the accuracy or co mpleteness of the contents of this document and reserves the rig ht to make changes to specifications and product descriptions at any time without notice. atmel does not make any commitment to update the information contained her ein. atmel?s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. atmel corporation atmel operations 2325 orchard parkway san jose, ca 95131, usa tel: 1(408) 441-0311 fax: 1(408) 487-2600 regional headquarters europe atmel sarl route des arsenaux 41 case postale 80 ch-1705 fribourg switzerland tel: (41) 26-426-5555 fax: (41) 26-426-5500 asia room 1219 chinachem golden plaza 77 mody road tsimshatsui east kowloon hong kong tel: (852) 2721-9778 fax: (852) 2722-1369 japan 9f, tonetsu shinkawa bldg. 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel: (81) 3-3523-3551 fax: (81) 3-3523-7581 memory 2325 orchard parkway san jose, ca 95131, usa tel: 1(408) 441-0311 fax: 1(408) 436-4314 microcontrollers 2325 orchard parkway san jose, ca 95131, usa tel: 1(408) 441-0311 fax: 1(408) 436-4314 la chantrerie bp 70602 44306 nantes cedex 3, france tel: (33) 2-40-18-18-18 fax: (33) 2-40-18-19-60 asic/assp/smart cards zone industrielle 13106 rousset cedex, france tel: (33) 4-42-53-60-00 fax: (33) 4-42-53-60-01 1150 east cheyenne mtn. blvd. colorado springs, co 80906, usa tel: 1(719) 576-3300 fax: 1(719) 540-1759 scottish enterprise technology park maxwell building east kilbride g75 0qr, scotland tel: (44) 1355-803-000 fax: (44) 1355-242-743 rf/automotive theresienstrasse 2 postfach 3535 74025 heilbronn, germany tel: (49) 71-31-67-0 fax: (49) 71-31-67-2340 1150 east cheyenne mtn. blvd. colorado springs, co 80906, usa tel: 1(719) 576-3300 fax: 1(719) 540-1759 biometrics/imagin g/hi-rel mpu/ high speed converters/rf datacom avenue de rochepleine bp 123 38521 saint-egreve cedex, france tel: (33) 4-76-58-30-00 fax: (33) 4-76-58-34-80 literature requests www.atmel.com/literature ? atmel corporation 2006 . all rights reserved. atmel ? , logo and combinations thereof, everywhere you, are ? avr ? , and others are registered trademarks or trademarks of atmel corporation or its subsidiaries. other terms and product names may be trademarks of others. |
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